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Reduced Wirelength-Based Low Power Performance of Multibit Flip-Flop

M.Karthick*, S. Vijayakumar**

*PG Scholar, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India.

**Associate Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, Namakkal, India.

Periodicity:September - November'2013
DOI : https://doi.org/10.26634/jcir.1.4.2593

Abstract

Power reduction is a main parameter to design VLSI circuits. In this paper, to design a number of D-flip flop performing at the same time, the given clock signal is reduced using multi bit flip-flop. The multi bit flip flop is mainly used to improve the clock power for the given common clock signal and to reduce the switching power. This method is performed to replace some D flip-flop into multi bit flip-flops with the given common clock input. In this proposed technique, first step is to identify the flip flops and its placed location, second step is to build the combination table mainly by merging the flip flop and removing the unwanted merging flip-flops, final step is to assign the region , place the flip flop in these flip-flops merging and replacing the merging location. By using this method, the result is used to reduce the power to 24mW and area by reducing to 35 gate count ,because this method considers the area measured as the number of gate count in the merging flip flop.

Keywords

Switching Power Reduction, Multi Bit Flip-flop, Merge and Clock Power.

How to Cite this Article?

Karthick, M. and Vijayakumar, S. (2013). Reduced Wire length-Based Low Power Performance Of Multibit Flip-Flop. i-manager’s Journal on Circuits and Systems, 1(4), 22-26. https://doi.org/10.26634/jcir.1.4.2593

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