Dynamic Simulation and Sensitivity Analysis of Steam Generation Solar Power Plant
Unified Power Quality Conditioner (UPQC) Research Study on Steady - State Power Flow
Photovoltaic Module Failure Detection using Machine Vision and Lazy Learning Technique
Design and Implementation of Wallace Tree Multiplier and Its Applications in FIR Filter
Review on Obstacle Detection in Solar Panel Cleaning Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Digital signals are crucial for transmission of information easily and securely. In digital scenario, Analog to Digital Converters (ADC) are essential for applications such as wireless communication and signal processing. Designing low power circuits that operate at low supply voltages operating at high speed plays an important role in VLSI. Among these circuits comparator is one. Comparators with high-speed, low power and reduced delay are important for faster operations in ADC. This paper presents the design of an improved Strong ARM latch comparator by reducing delay time for enhancing its speed of operation. Comparative analysis for proposed design in terms of various parameters including power, energy per conversion, delay, speed, offset and power-delay product are presented. Delay Comparison for different dynamic comparators are performed. The standard deviation of the input-referred offset for proposed design is 8.81mV at 1V supply. The proposed dynamic comparator is faster and consumes less power. At a clock frequency of 0.2 GHz and 1 mV.
This paper presents feedback linearization technique based Direct Power Control (DPC) algorithm for 3-phase Voltage Source Inverter (VSI). In order to make the controller design easy and independent of the operating point, the non-linear model of the VSI is transferred into linear model. The Direct Power Control - Space Vector Modulation (DPC-SVM) technique is adopted and the problem is formulated in DPC framework in which the constant switching frequency is maintained throughout the operation of the Inverter. A robust nonlinear controller for DPC-VSI applying Input-Output linearization (IOL) techniques is also discussed. To cancel the non linearities and to decouple the input control variables, the feedback linearization nonlinear technique is used. Great tracking capability with zero steady-state of the voltage loop has been achieved by zero-dynamic control. Also, there is no derivative calculation required and measurement of load current is not needed. The controller which is proposed in this paper has advantages of fast DC-bus voltage response, robust against parameter uncertainties and decoupled dynamical d-q current loops which provide wide operating range and fast transient responses. The validity of the technique has been verified through experimental setup which is compared with the traditional control. The results analysis shows that the use of feedback linearization control gives excellent transient response both during balanced and unbalanced load and with gird voltage.
In recent trends, the industry and most researchers are focusing on the scale down of CMOS technologies to improve the speed and leakage power reduction in the circuits. These unsought leakage currents should be minimized for smooth functioning of the circuits. To develop such type of leakage-free CMOS circuits could be challenging. The main objective of the project is to address the issues over leakage power reductions, delay and efficiency. We present a circuit technique for mitigating MOSFET through controlling the voltage at source terminal of the MOSFET. In this paper we will present CMOS INVERTER, NAND, NOR, XOR using Lector technique. The simulation results are obtained with the aid of MENTOR GRAPHICS of 120 nm technology and also the comparisons of power dissipation by using with and without Lector techniques and with other techniques.
The fundamental operation in digital signal processing and wireless signal processing applications like Multiple Input and Multiple Output (MIMO), Orthogonal Frequency Division Multiple Access (OFDM) is a Fast Fourier Transform(FFT). FFT is the fastest way of computing Discrete Fourier Transform by way of Divide and Conquer technique. There are different ways of developing VLSI architecture for FFT processor by using Delay elements (SDF, MDF), Delay Commutators (SDC, MDC). The famous architecture for FFT processor is Single Delay Feedback (SDF) architecture which has an advantage of full (100%) hardware utilization. Another famous architecture known as Multipath Delay Commutator (MDC) has an advantage high throughput at 50% of hardware utilization. In this project, we propose VLSI hardware architecture for twin data stream processing using Radix-2 algorithm. The proposed architecture is based on pipelined MDC architecture. The proposed architecture uses both Decimation-In-Time FFT (DIT-FFT) and Decimation-In-Frequency FFT (DIF-FFT) to process even and odd samples of twin data streams. In this architecture the bit reversal operation is carried out by the proposed architecture itself. When compare to other exiting architecture to proposed work designed with shift registers, bit reverserval operation performed in FFT with a high throughput and less numbers of registers.
