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Analysis, Design and Performance Comparison of Strongarm Latch Comparator

G. Appala Naidu*, N. Maheswari**

* Department of Systems and Signal processing, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

** Department of Electronics and Communication Engineering, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

Periodicity:September - November'2019
DOI : https://doi.org/10.26634/jcir.7.4.17110

Abstract

Digital signals are crucial for transmission of information easily and securely. In digital scenario, Analog to Digital Converters (ADC) are essential for applications such as wireless communication and signal processing. Designing low power circuits that operate at low supply voltages operating at high speed plays an important role in VLSI. Among these circuits comparator is one. Comparators with high-speed, low power and reduced delay are important for faster operations in ADC. This paper presents the design of an improved Strong ARM latch comparator by reducing delay time for enhancing its speed of operation. Comparative analysis for proposed design in terms of various parameters including power, energy per conversion, delay, speed, offset and power-delay product are presented. Delay Comparison for different dynamic comparators are performed. The standard deviation of the input-referred offset for proposed design is 8.81mV at 1V supply. The proposed dynamic comparator is faster and consumes less power. At a clock frequency of 0.2 GHz and 1 mV.

Keywords

ADCs, Strong ARM, Offset, Dynamic Comparators, CMOS Technology, Cadence Virtuoso.

How to Cite this Article?

Maheswari, N., and Naidu, G. A. (2019). Analysis, Design and Performance Comparison of Strongarm Latch Comparator. i-manager's Journal on Circuits and Systems , 7(4), 1-9. https://doi.org/10.26634/jcir.7.4.17110

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