i-manager's Journal on Circuits and Systems (JCIR)


Volume 3 Issue 4 September - November 2015

Research Paper

Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design

James Edward Osler II*
James Edward Osler II  
Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.
Osler, J. E., II. (2015). Trichotomous Charge States: The Novel Trioinformatics Application of Neuroengineering Neuromathematics Notation to Express and Expound Polyphase Electrical Systems and Tri-State Buffers for Digital Circuit Design. i-manager’s Journal on Circuits and Systems, 3(4), 1-19. https://doi.org/10.26634/jcir.3.4.5926

Abstract

The narrative in this discourse provides the third part of an epistemological rational for the novel discipline of “Trioinformatics”. This novel application of trioinformatic notation in mathematical form is the continuation of the Trioinformatics article that appeared in the March–May i-manager’s Journal on Circuits and Systems,“Trichotomous Charge States” [denoted by the acronym “TCS”] use “Neuroengineering Neuromathematics Notation” as the explicative expression of Trioinformatics in “Polyphase Electrical Systems” and electronic “Tri–State Buffers”. Trioinformatics Neuroengineering also has broad applications when used as an innovative way of explaining the transition from trichotomous logic (Osler, 2015) into trichotomous Triple–I (Osler, 2013d) research questions and associated instrumentation [first introduced in the i-manager’s Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012a)]. Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational technique for explaining the ternary properties of electronic circuitry (Osler, 2015). The use of Trioinformatics also adds value to investigative inquiry through the efficacy of digital instruments and tools via eduscientifically–engineered (Osler, 2013) research designs (Osler, 2015). Additional research into trioinformatics and its neuroengineered neuromathematical notation will further advance in–depth investigations into the tripartite aspects of digital instrumentation and digital / electronic circuitry.

Research Paper

Performance Analysis of Fly-Back Converter Using Photovoltaic Cells

Vikash Kumar Rai* , Krishna Pratap Singh**
* PG Scholar, Department of Power Electronics and Drives, Madan Mohan Malviya University of Technology, Gorakhpur, India.
** Associate Professor, Department of Electrical Engineering, Madan Mohan Malviya University of Technology, Gorakhpur, India.
Rai, V. K., and Singh, K. P. (2015). Performance Analysis of Fly-Back Converter Using Photovoltaic Cells. i-manager’s Journal on Circuits and Systems, 3(4), 20-27. https://doi.org/10.26634/jcir.3.4.5927

Abstract

Solar energy systems based on photovoltaic (PV) cells have attracted a considerable interest in recent years due to their free and easily available nature and promise related clean energy. Non-renewable energy resources like coal, nuclear, petroleum gas, diesel, etc., are depleting and hazardous to our environment too. There are two types of converter techniques used in the photovoltaic system, first is the single-stage converter technique and second is the two-stage converter technique. This two-stage converter technique uses photovoltaic cells. In the first stage, a fly-back DC to DC converter is used, while in the second stage, are SPWB based inverter is used. Its performance is discussed and compared with the boost converter based photovoltaic cell, for which MPPT based photovoltaic cells are used. For achieving better performance, a Sinusoidal Pulse Width Modulation (SPWM) technique is also used.

Research Paper

Performance Analysis of Wind Turbines with DFIG for Low Voltage Ride Through Capability Using a Crowbar Device

Mitali Gupta* , Ashok Kumar Pandey**
* PG Scholar, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India.
** Associate Professor, Department of Electrical Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, India.
Gupta, M., and Pandey, A. K. (2015). Performance Analysis of Wind Turbines with DFIG for Low Voltage Ride Through Capability Using a Crowbar Device i-manager’s Journal on Circuits and Systems, 3(4), 28-36. https://doi.org/10.26634/jcir.3.4.5928

Abstract

Now-a-days, the penetration level of the wind generator system directly connected to the power system grid is rapidly increasing. Doubly Fed Induction Generator has been broadly used in Variable-Speed Constant-Frequency (VSCF) wind energy generation systems. The Doubly Fed Induction Generator (DFIG) based wind turbine system provides considerably better power delivery towards the demand. In this paper, the performance of DFIG based WT system during various types of symmetrical and unsymmetrical fault has been discussed. LVRT capability of the system based on the grid connection requirement during these faults is studied and discussed here. In this paper, a Crowbar protection device is discussed to overcome the undervoltage and overcurrent phenomenon.

Research Paper

A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption

C. Ruth Vinutha* , M. Bharathi**, D. Divya***
*,*** PG Scholar, Department of Electronics and Communication Engineering, SVEC, Tirupati, Chitoor, India.
** Assistant Professor, Department of Electronics and Communication Engineering, SVEC, Tirupati, Chitoor, India.
Vinutha, C. R., Bharathi, M., and Divya, D. (2015). A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption. i-manager’s Journal on Circuits and Systems, 3(4), 37-41. https://doi.org/10.26634/jcir.3.4.5929

Abstract

The Parallel Prefix Adder (PPA) is one of the fastest type of adders that had been created and developed from carry look ahead adders. Three common types of parallel prefix adders are Brent-Kung, Han-Carlson and Kogge-Stone adders. This research involves an investigation of the performances of these three adders in terms of computational delay, Power, Speed and design area. The investigation and comparison for these adders was conducted for a 16 bit size. By using the Xilinx 14.5 design software, the designs for Brent Kung, Han-Carlson and Kogge Stone adders were developed. Comparison of area, delay, speed and area for 16 bit Kogge Stone, Han-Carlson and Brent Kung adders show that the Kogge Stone adder is best in terms of speed and the reduced area is obtained from the Han-Carlson adder. The results and simulation are verified using Xilinx 14.5 software.

Research Paper

Parallel Prefix Adder Using Static Conventional Logic Gates

D. Divya* , M. Bharathi**, C. Ruth Vinutha***
*,*** PG Scholar, Department of Electronics and Communication Engineering, SVEC, Tirupati, Chitoor, India.
** Assistant Professor, Department of Electronics and Communication Engineering, SVEC, Tirupati, Chitoor, India.
Divya, D., Bharathi, M., and Vinutha, C. R. (2015). Parallel Prefix Adder Using Static Conventional Logic Gates. i-manager’s Journal on Circuits and Systems, 3(4), 42-47 https://doi.org/10.26634/jcir.3.4.5930

Abstract

An adder is a device, that adds two numbers and generates the summed result. In digital circuits, there are so many adders like carry select adder, ripple carry adder, carry skip adder, ling adder, manchester carry-chain adder and so on. Among all adders, parallel prefix adder is a highly-efficient binary adder. These parallel prefix adders are implemented in a new topology called Static Null Conventional Logic (NCL) gates. NCL gates are asynchronous circuits which are independent of the clock skew problem, delay and consumes less power. The static implementation of conventional versions of NCL gates use a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. Implementation of parallel prefix in NCL gates, increase the area overhead problems that occur, but the power consumption reduces due to connecting and disconnecting of the specified gate terminal.