Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
The narrative in this discourse provides the third part of an epistemological rational for the novel discipline of “Trioinformatics”. This novel application of trioinformatic notation in mathematical form is the continuation of the Trioinformatics article that appeared in the March–May i-manager’s Journal on Circuits and Systems,“Trichotomous Charge States” [denoted by the acronym “TCS”] use “Neuroengineering Neuromathematics Notation” as the explicative expression of Trioinformatics in “Polyphase Electrical Systems” and electronic “Tri–State Buffers”. Trioinformatics Neuroengineering also has broad applications when used as an innovative way of explaining the transition from trichotomous logic (Osler, 2015) into trichotomous Triple–I (Osler, 2013d) research questions and associated instrumentation [first introduced in the i-manager’s Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012a)]. Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational technique for explaining the ternary properties of electronic circuitry (Osler, 2015). The use of Trioinformatics also adds value to investigative inquiry through the efficacy of digital instruments and tools via eduscientifically–engineered (Osler, 2013) research designs (Osler, 2015). Additional research into trioinformatics and its neuroengineered neuromathematical notation will further advance in–depth investigations into the tripartite aspects of digital instrumentation and digital / electronic circuitry.
Solar energy systems based on photovoltaic (PV) cells have attracted a considerable interest in recent years due to their free and easily available nature and promise related clean energy. Non-renewable energy resources like coal, nuclear, petroleum gas, diesel, etc., are depleting and hazardous to our environment too. There are two types of converter techniques used in the photovoltaic system, first is the single-stage converter technique and second is the two-stage converter technique. This two-stage converter technique uses photovoltaic cells. In the first stage, a fly-back DC to DC converter is used, while in the second stage, are SPWB based inverter is used. Its performance is discussed and compared with the boost converter based photovoltaic cell, for which MPPT based photovoltaic cells are used. For achieving better performance, a Sinusoidal Pulse Width Modulation (SPWM) technique is also used.
Now-a-days, the penetration level of the wind generator system directly connected to the power system grid is rapidly increasing. Doubly Fed Induction Generator has been broadly used in Variable-Speed Constant-Frequency (VSCF) wind energy generation systems. The Doubly Fed Induction Generator (DFIG) based wind turbine system provides considerably better power delivery towards the demand. In this paper, the performance of DFIG based WT system during various types of symmetrical and unsymmetrical fault has been discussed. LVRT capability of the system based on the grid connection requirement during these faults is studied and discussed here. In this paper, a Crowbar protection device is discussed to overcome the undervoltage and overcurrent phenomenon.
The Parallel Prefix Adder (PPA) is one of the fastest type of adders that had been created and developed from carry look ahead adders. Three common types of parallel prefix adders are Brent-Kung, Han-Carlson and Kogge-Stone adders. This research involves an investigation of the performances of these three adders in terms of computational delay, Power, Speed and design area. The investigation and comparison for these adders was conducted for a 16 bit size. By using the Xilinx 14.5 design software, the designs for Brent Kung, Han-Carlson and Kogge Stone adders were developed. Comparison of area, delay, speed and area for 16 bit Kogge Stone, Han-Carlson and Brent Kung adders show that the Kogge Stone adder is best in terms of speed and the reduced area is obtained from the Han-Carlson adder. The results and simulation are verified using Xilinx 14.5 software.
An adder is a device, that adds two numbers and generates the summed result. In digital circuits, there are so many adders like carry select adder, ripple carry adder, carry skip adder, ling adder, manchester carry-chain adder and so on. Among all adders, parallel prefix adder is a highly-efficient binary adder. These parallel prefix adders are implemented in a new topology called Static Null Conventional Logic (NCL) gates. NCL gates are asynchronous circuits which are independent of the clock skew problem, delay and consumes less power. The static implementation of conventional versions of NCL gates use a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. Implementation of parallel prefix in NCL gates, increase the area overhead problems that occur, but the power consumption reduces due to connecting and disconnecting of the specified gate terminal.
