Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
The Multiplier-and-Accumulator (MAC) unit is the basic element of the digital signal processing(DSP) applications such as filtering, convolution, transformations and Inner products. So the MAC should provide high speed multiplication and multiplication with accumulative addition. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products. The objective of the paper is to reduce the power consumption using Modified Booth Algorithm and Spurious Power Suppression Technique. And also to increase the speed of operation by decreasing the number of MAC stages. By using radix-4 Modified Booth Algorithm, partial products are reduced by half and then by using Spurious Power Suppression Technique power has been reduced. In this architecture, multiplication and accumulation have been combined with a hybrid type of Carry Save Adder (CSA). In booth multiplication, when two numbers are multiplied, some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose, Spurious Power Suppression Technique (SPST) is used to remove ineffective portion of the data in addition process. The modified MAC operation is coded with Verilog and simulated using Xilinx ISE 12.1.
Fused Multiply Add (FMA) units generally reduce delay in the overall circuit and also make it efficient in terms of energy in arithmetic operations. In this paper, the authors present an effective implementation of MFMA (Modified FMA) using pipelining by decreasing the delay compared to the parallel processing of the module. This MFMA uses two desperate Massif which are connected using pipelining. The final operation performed is A*B+C*D+F*G+H*I, parallel processing just implements unto A*B+C*D. The clock limiting stage for both these operations is involved in normalization stage and rounding stage. This paper is related to floating point calculations. Floating point calculations involve, a standard format for representing floating point numbers. The standard format for representing floating point numbers is IEEE 754- 2008.This floating point representation is used here. In this paper the pipelining implementation is mainly related to speed, i.e., delay of the circuit. This paper can be designed using trilogy HDL or VHDL and is simulated and synthesized in XILINX ISE 10.1 of FPGA.
As technology scales down, the leakage power becomes dominant due to the second order effects of the transistors. The leakage power aids in considerable increase of the total power dissipation of the device. The existing SRAM cells at submicron region dissipate more power and become in stable in spite of applying low power techniques like multithreshold logic, body biasing techniques, stacked structures etc. This paper concentrates on low power highly stable SRAM cell using only five transistors and a low power technique called Gated Bias Technique. In this paper, the schematics are developed using Digital Schematic Tool and the corresponding layouts are developed using Microwind Tool. The designs are optimized for low area with good stability and low power dissipation. Further they are compared for various Technologies downline from 180nm to 90nm.
Work presented in this paper is fuzzy logic based Water Heater Demand Controller considering the consumer preferences and desires. A fuzzy controlled intelligent system is proposed, which conserves the electrical energy in case of water heating solutions. In modern days, consumers demand more pricing and usage operations making load management programs increasingly prevalent. A methodology is proposed to reduce the usage of the electrical energy based on needs and comfort. Thereby, the demand on the power system can be reduced during peak hours with the help of load management programs. The most popular load management program is End-Use Equipment Control. It is also called as Direct Load Control. DLC is used to shape the load curve by cycling consumer's large current drawing appliance, like water heaters. This paper presents the application of DSM techniques to Water Heater Demand Controller to limit the power consumption based on consumer choice and satisfaction. Results presented are to show the effectiveness of the proposed intelligent water heater demand controller to minimize the energy consumption, reduce the energy bill and satisfy consumer needs based on environmental conditions/seasons.
Microwave radar requires the development of pulse generators that are capable of producing a succession of pulses in very short time durations. The generation of radar transmitter requires high-power and high-voltage pulses, whereas the indicator and ranging circuits require pulses of negligible power and relatively low voltage. This paper presents a pulse generator which is designed by using edge generator circuit with edge tuning capability. The pulse generator circuit obtained generates the pulses dissipating power which is less when compared to CMOS (Complementary Metal Oxide Semiconductor) logic. It is an energy efficient circuit which can be implemented in HSPICE using 0.18μm CMOS standard process technology.
