Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
In this paper, the authors present an efficient implementation of Floating point multiplier which decreases delay of the circuit and this is done by replacing the multiplier block in the floating point multiplier and by comparing the delays in multiplication for each and every multiplier. In this paper, they use a standard floating point format i.e., IEEE 754 (which is a common standard for both Single Precision and Double Precision Floating point multipliers). Floating Point multiplication is an important factor in most DSP Applications. The other requirement of DSP applications in their fabrication is less area and low power consumption and less delay, also the performance matters in DSP systems. DSP systems require high performance. In this paper, the authors relate all the requirements of the DSP applications with respect to its speed. They have compared various multipliers as said before and have produced the best multiplier for floating point multiplication in terms of speed. This paper can be implemented using verilog HDL or VHDL and is checked in XILINX ISE 10.1 of FPGA.
This paper presents a new system configuration of the front-end rectifier stage for a hybrid wind/photovoltaic energy system. This configuration allows the two sources to supply the load separately or simultaneously depending on the availability of the energy sources. The inherent nature of this Cuk-SEPIC fused converter, is that, additional input filters are not necessary to filter out high frequency harmonics. Harmonic content is detrimental for the generator lifespan, heating issues, and efficiency. The fused multi input rectifier stage also allows Maximum Power Point Tracking (MPPT) to be used to extract maximum power from the wind and sun when it is available. An adaptive MPPT algorithm will be used for the wind system and a standard perturb and observe method will be used for the PV system. Operational analysis of the proposed system will be discussed in this paper. Simulation results are given to highlight the merits of the proposed circuit.
This paper proposes an effective Fault Detection Technique in distance relaying using discrete current samples. The original signal under fault consists of two parts namely, normal and disturbance part. The fault detection is easily achieved as the disturbance part of the signal produces an irregular shape compared to the shape produced from the normal part of the signal. By selecting suitable threshold value, the starting point of irregular part can be found. The proposed algorithm is so effective and easy when compared to other algorithms. Results are carried out in MATLAB/SIMULINK software.
The DC performance of the Quantum Dot Transistor under illumination is studied and presented in this paper. A device structure consisting of Quantum Dots(QD) in the GaAs layer is considered for illumination. The photoconductive effect in the GaAs and QD layer which increases the 2DEG Channel electron concentration is considered. The I-V Characteristics of Quantum Dot Transistor, under dark and illumination condition have been calculated, plotted and discussed. The Transfer Characteristics of Quantum Dot Transistor without and with illumination, Optical Response of Quantum Dot Transistor, and sheet concentration of the device is also calculated, plotted and discussed.
In this paper, an attempt to overcome the challenges in catenary wire protection, using the distance protection techniques has been made. A nano superhydrophobic coating is coated on the aluminum rod and copper plate, and the coating was showing an insulation property which can control few amount of transformer impedance to inject into the catenary line and can control dynamic variation of impedance which is discussed with a simple experiment in this paper. This even acts as a self-cleaning superhydrphobicity as 'natural lotus effect'.
Distance protection relays utilize the comparison of the measured impedance with the set impedance, and the result is utilized to decide, whether a fault has occurred or not. When a fault occurs, the magnitude of current increases, and that of the voltage decreases which results in a dip in impedance. When the measured impedance is lesser than the set impedance, then the distance protection relay will trip the breaker. This concept is perfect in most of the applications, but in catenary wire protection, the set impedance varies dynamically. The dynamic variation of the set impedance is due to the movement of electric locomotives where the locomotive transformer gets included in the circuit dynamically. The theoretical solution towards this concept is proposed in this paper.
