Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Recent regulations have demanded that electronics manufacturing companies control emissions from their products and the susceptibility of their products for Emissions from other products. In addition, unexpected product failure and the ever-present demands of technology are also forcing the electronics industry to face the need to maintain Electrical Integrity. The investigations into high-speed design techniques have shown three major causes of failure: emissions from interconnecting conductors; poor PCB layout and lack of technical knowledge in Electro Magnetic Compatibility (EMC). Catching these kinds of electrical integrity problems early in the design phase allows designers to take timely action without jeopardising project time scales. The work reported here presents design for manufacturing guidelines and rules to maintain electrical integrity in Printed Circuit Boards (PCBs). Currently, a common method for handling EMC is through compliance testing of the final product. Similarly, noise budget is measured on finishing prototypes. Since product life cycles are reduced, dealing with EMC late in the design cycle is undesirable. The cost of fixing may also be higher at a final stage because only a few options are available to correct the problem. A 'find and fix' approach is no longer acceptable. More and more companies are facing or will soon be facing EMC and electrical integrity issues. The majority of analysis tools available today are targeted towards simulation engineers. Such tools are not easy to use and are dependent on the availability and accuracy of complex simulation models. Moreover, they also tend to be ineffective on how to correct potential EMC problems.
An improved three level inverter scheme, with less number of switches, having the features of common mode voltage elimination, DC link capacitor voltage balancing, and minimization and equalization of voltage stress across the switches, for an open end winding induction motor drive, have been proposed in this paper. Open-end winding induction motor, when fed from its two ends by a three level inverter, suffers from the drawbacks of common mode voltage, which causes current to flow through its bearings along with the shaft and that type of capacitor voltage unbalance, causes current to flow through the neutral point. Further, such inverters require a large number of switches, which lead to higher switching losses and unequal voltage stress in the switches. A new inverter topology with less number of switches, that gets rid of the problems of common mode voltage and DC link capacitor voltage unbalance along with reduced and equalized voltage stresses in the switches, has been proposed in this paper. The simulation and the hardware results of the proposed topology show smoother output voltages across the machine phases.
This paper suggests an active power filter implemented with a four leg voltage-source inverter using DQ (Synchronous Reference Frame) based Current Reference Generator scheme. The use of a four-leg voltage-source inverter allows the compensation of current harmonic components, as well as unbalanced current generated by single-phase non-linear loads. The grid interfacing can thus be utilized as:1) Power Converter to inject power generated from rest of the grid, and 2) Shunts APF to current unbalance, load current harmonics and load reactive power demand. The compensation, performance of the proposed active power filter using an adaptive fuzzy controller and the associated control scheme under steady state and transient operating conditions are demonstrated through simulation results.
This paper evaluates the performance of a fuzzy based power flow control of grid connected hybrid system. The hybrid system composed of a Photo Voltaic (PV) array and a Proton Exchange Membrane Fuel Cell (PEMFC) is considered. The Photo Voltaic (PV) array normally uses a Maximum Power Point Tracking (MPPT) technique to continuously deliver the highest power to the load when there are variations in irradiation and temperature which make it become an uncontrollable source. In coordination with PEMFC, the hybrid system output power becomes controllable. Two operation modes, the Unit -Power Control (UPC) mode and the Feeder-Flow Control (FFC) mode, can be applied to the hybrid system. In the UPC mode, variations in load demand are compensated by the main grid because the hybrid source output is regulated to reference power by using an adaptive fuzzy controller. The proposed operating strategy with a flexible operation mode change always operates the PV array at maximum output power and the PEMFC in its high efficiency performance band, thus improving the performance of system operation, enhancing system stability, and decreasing the number of operating mode changes. This new control concept is demonstrated with extensive MATLAB/Simulink simulation studies.
Conventional Combinational logic circuits dissipate heat for every bit of information that is lost during their operation. Due to this fact the information once lost cannot be recovered in any way. A reversible logic gate is a n-input, n-output logic device which helps to determine the outputs from the inputs but also the inputs can be recovered from the outputs. Extra inputs or outputs are added so that the number of inputs is made equal to the number of outputs whenever it is necessary. For reversible computer the heat dissipation is logically 0. Therefore, in upcoming high performance it is considered as the promising technology at low power consumption. Therefore, there is requirement of designing reversible gates. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. The proposed techniques overcome the shortcoming of the present techniques like garbage output, delay and quantum cost and efficiency in designing the circuit which can be performed effectively by increasing the performance and reducing the delays with the same power consumption. It also reduces the no of flip flops, and gates which reduces the memory size and area.
