i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 12 Issue 1

Unified Power Quality Conditioner Research Study on STEADY - STATE POWER FLOW

Most Cited

Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Volume 10 Issue 2 July - December 2022

Research Paper

An Innovative FPGA-Based ADC/DAC Design using 1-Bit Adaptive-Delta Modulation

Akash Sardar* , Sayantan Dey, Iti Saha Misra*

*-*** Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India.

Sardar, A., Dey, S., and Misra, I. S. (2022). An Innovative FPGA-Based ADC/DAC Design using 1-Bit Adaptive-Delta Modulation. i-manager’s Journal on Circuits and Systems, 10(2), 1-9. https://doi.org/10.26634/jcir.10.2.18902

Abstract

The Analog-to-Digital Converter (ADC), with its wide variety of applications in the electronics and communication domains, is the most crucial unit in every digital gadget. This paper discusses a smart way of converting an input analog signal to its digital counterpart using an innovative Adaptive-Delta modulator, followed by a signal reconstruction process to retrieve the original message. It has done the design in Matrix Laboratory (MATLAB) Simulink, and the hardware implementation is tested on the Xilinx Spartan-6 LX45 FPGA core. This design aims for high-accuracy conversion and optimization of hardware resources. The 1-bit adaptive model is superior in comparison to the traditional delta modulation (DM) scheme while tracking stiff analog input signals, producing a much lower mean square error. The implementation is quite simple as it uses the transmission of 1-bit digital data at a time. On the receiver side, digital-toanalog conversion (DAC) makes use of the same adaptive logic in reconstructing the original input signal. The designed prototype demonstrates its resistance to a wide range of input amplitude and frequency variations. The ADC-DAC design method in this paper is accurate, makes the best use of resources, and is easy to use.

References

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[4]. Baig, M. N. A., & Ranjan, R. (2017). Design and implementation of 3-bit high speed flash ADC for wireless LAN applications. International Journal of Advanced Research in Computer and Communication Engineering, 6(3), 428-433. https://doi.org/10.17148/IJARCCE.2017.6399

[5]. Dalmia, H., & Sinha, S. K. (2020). Analog to digital converters (ADC): A literature review. In E3S Web of Conferences, 184, Article 01025. https://doi.org/10.1051/e3sconf/202018401025

[6]. Firojuddin, S., Pal, S., & Pain, P. (2020). Design and comparative analysis of low-power, high-speed, 3-bit flash ADC for biomedical signal processing using 45-nm CMOS technology. In K. Maharatna, M. Kanjilal, S. Konar, S. Nandi, K. Das, (Eds.) Computational Advancement in Communication Circuits and Systems, (pp. 331-342). https://doi.org/10.1007/978-981-13-8687-9_30

[7]. Jammu, B. R., Botcha, H. K., Sowjanya, A. V., & Bodasingi, N. (2017, April). FPGA implementation of BASKBFSK- BPSK-DPSK digital modulators using system generator. In 2017, International Conference on Ciruit, Power and Computing Technologies (ICCPCT) (pp. 1-5). IEEE. https://doi.org/10.1109/ICCPCT.2017.8074203

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[9]. Kaur, S., & Charanjit, S. (2013). FPGA implementation of sigma delta ADC on Spartan 2. International Journal of Advanced Research in Computer and Communication Engineering, 2(10), 4168-4172.

[10]. Kumar, N., Rawat, M., & Rawat, K. (2020). Softwaredefined radio transceiver design using FPGA-based system-on-chip embedded platform with adaptive digital predistortion. IEEE Access, 8, 214882-214893. https://doi.org/10.1109/ACCESS.2020.3041463

[11]. Li, H., & Hu, J. (2019, October). The research on SAR ADC integrated circuit. Journal of Physics: Conference Series, 1314(1), Article 012022. https://doi.org/10.1088/1742-6596/1314/1/012022

[12] . Ndzi, D. L., Stuart, K., Toautachone, S., Yang, Y., & Dunn, V. (2011). An FPGA-based adaptable 200 MHz bandwidth channel sounder for wireless communication channel characterisation. International Journal of Reconfigurable Computing, 2011, Article 894530. https://doi.org/10.1155/2011/894530

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[14]. Popescu, S. O., Gontean, A. S., & Budura, G. (2011, May). Simulation and implementation of a BPSK modulator on FPGA. In 2011, 6th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI) (pp. 459-463). IEEE. https://doi.org/10.1109/SACI.2011.5873047

[15]. Shende, R. M., & Gumble, P. R. (2011). VLSI design of low power high speed 4 bit resolution pipeline ADC in submicron CMOS technology. International Journal of VLSI Design & Communication Systems, 2(4), 81–93. https://doi.org/10.5121/vlsic.2011.2408

[16]. Zhang, H. F., Luo, C. L., Tang, P. Y., Cui, K., Lin, S. Z., Jin, G., & Wang, J. (2013, October). High-speed arbitrary waveform generator based on FPGA. In 2013, IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC) (pp. 1-5). IEEE. https://doi.org/10.1109/NSSMIC.2013.6829760

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Research Paper

THD Analysis and Stability Enhancement of PID Controller in SRF-Based Shunt Active Filter under Different Design Criteria using GWO Technique

Nidhi Sahu* , Sandeep Sahu, Pushpa Sahu*

- Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India.

Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Durg, Chhattisgarh, India.

Sahu, N., Sahu, S., and Sahu, P. (2022). THD Analysis and Stability Enhancement of PID Controller in SRF-Based Shunt Active Filter under Different Design Criteria using GWO Technique. i-manager’s Journal on Circuits and Systems, 10(2), 19-27. https://doi.org/10.26634/jcir.10.2.18912

Abstract

Power electronic devices are essential to industrial processes, research, and development, it provides high efficiency, low cost, fast operation, and ideal dimensions. Power systems are significantly affected by harmonics, which are mainly generated by non-linear loads and power conversion technologies, including static converters, breakers, cycloconverters, battery charging systems, and heating components. Various filtering methods are available for harmonic suppression, among which the active power shunt filter is one of the most significant and effective. Harmonics are suppressed and system efficiency is improved using the Grey Wolf Optimization (GWO) approach. The design criteria are integrated into the cost function itself. Using various design criteria, the performance of a shunt active power filter is investigated. The design criteria used are Integral square error (ISE), Integral absolute error (IAE), Integral time absolute error (ITAE), and Integral time square error (ITSE) with ITAE having the best performance.

References

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[13]. Monfared, M., Golestan, S., & Guerrero, J. M. (2013). A new synchronous reference frame- based method for single-phase shunt active power filters. Journal of Power Electronics, 13(4), 692-700. https://doi.org/10.6113/JPE.2013.13.4.692

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[15]. Rao, B. C., Sahu, P., & Jhapte, R. (2022, April). Comparative analysis of SRF based shunt active filter using grey wolf and eagle perching optimization. In 2022, Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), (pp. 1-7). IEEE. https://doi.org/10.1109/ICAECT54875.2022.9807876

[16]. Rodriguez, P., Pou, J., Bergas, J., Candela, J. I., Burgos, R. P., & Boroyevich, D. (2007). Decoupled double synchronous reference frame PLL for power converters control. IEEE Transactions on Power Electronics, 22(2), 584- 592. https://doi.org/10.1109/TPEL.2006.890000

[17]. Salim, C., & Toufik, B. M. (2011). Intelligent controllers for shunt active filter to compensate current harmonics based on SRF and SCR control strategies. International Journal on Electrical Engineering and Informatics, 3(3), 372-393.

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[19]. Solihin, M. I., Tack, L. F., & Kean, M. L. (2011, January). Tuning of PID controller using particle swarm optimization (PSO). In Proceeding of the International Conference on Advanced Science, Engineering and Information Technology, (pp. 458-461).

[20]. Zaveri, N., Mehta, A., & Chudasama, A. (2009, December). Performance analysis of various SRF methods in three phase shunt active filters. In 2009, International Conference on Industrial and Information Systems (ICIIS), (pp. 442-447). IEEE. https://doi.org/10.1109/ICIINFS.2009.5429819

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Research Paper

Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop

Varun* , Bal Krishan, Rohit Tripathi*

*-*** Department of Electronics Engineering, YMCA University of Science and Technology, Faridabad, Haryana, India.

Varun, Krishan, B., and Tripathi, R. (2022). Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop. i-manager’s Journal on Circuits and Systems, 10(2), 10-18. https://doi.org/10.26634/jcir.10.2.18978

Abstract

In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.

References

[1]. Aguirre-Hernandez, M., & Linares-Aranda, M. (2006, April). A clock-gated pulse-triggered D flip-flop for lowpower high-performance VLSI synchronous systems. In 2006, International Caribbean Conference on Devices, Circuits and Systems, (pp. 293-297). IEEE. https://doi.org/10.1109/ICCDCS.2006.250876

[2]. Asthana, A., & Akashe, S. (2013). Power efficient d flip flop circuit using MTCMOS technique in deep submicron technology. International Journal of Engineering Research & Technology, 2(11), 1785-1791.

[3]. Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4), 473-484. https://doi.org/10.1109/4.126534

[4]. Deepthi, K., & Srikanth, M. P. (2019). Design of 18- transistor TSPC Flip-Flop based on logic structure reduction schemes. International Journal of Research, 8(5), 1049-1056.

[5]. Kavali, K., Rajendar, S., & Naresh, R. (2015). Design of low power adaptive pulse triggeredflip-flop using modified clock gating schemeat 90nm technology. Procedia Materials Science, 10, 323-330. https://doi.org/10.1016/j.mspro.2015.06.063

[6]. Kim, S. H., & Mooney, V. J. (2006, October). Sleepy keeper: a new approach to low-leakage power VLSI design. In 2006, IFIP International Conference on Very Large Scale Integration, (pp. 367-372). IEEE. https://doi.org/10.1109/VLSISOC.2006.313263

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[8]. Kumar, K. V. K. V. L. P., Prabhakar, V. S. V., Naresh, K., Krishna, N. G., & Hari, R. S. (2021). Design and analysis of FS-TSPC-DET flip-flop for IoT applications. Turkish Journal of Computer and Mathematics Education, 12(5), 161-169. https://doi.org/10.17762/turcomat.v12i5.808

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[11]. Pedram, M. (2003). Power minimization in IC design: Principles and applications. ACM Transactions on Design Automation of Electronic Systems (TODAES), 1(1), 3-56. https://doi.org/10.1145/225871.225877

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[13]. Powell, M., Yang, S., Falsafi, B., Roy, K. & Vijaykumar, T. N. (2000). Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the 2000 International Symposium on Low Power Electronics and Design (ISLPED'00), (pp. 90-95). https://doi.org/10.1109/LPE.2000.155259

[14]. Razavi, B. (2016). TSPC logic [a circuit for all seasons]. IEEE Solid-State Circuits Magazine, 8(4), 10-13. https://doi.org/10.1109/MSSC.2016.2603228

[15]. Roy, K., Mukhopadhyay, S., & Mahmoodi- Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305-327. https://doi.org/10.1109/JPROC.2002.808156

[16]. Shaikh, J., & Rahaman, H. (2018, March). High speed and low power preset-able modified TSPC D flipflop design and performance comparison with TSPC D flip-flop. In 2018, International Symposium on Devices, Circuits and Systems (ISDCS), (pp. 1-4). IEEE. https://doi.org/10.1109/ISDCS.2018.8379677

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Research Paper

A Novel Multiplication Design Based on LUT Method

Tharun Kumar Reddy M.* , M. Bharathi, N. Padmaja*, B. Ashreetha****

*-**** Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.

Reddy, M. T. K., Bharathi, M., Padmaja, N., and Ashreetha, B. (2022). A Novel Multiplication Design Based on LUT Method. i-manager’s Journal on Circuits and Systems, 10(2), 28-34. https://doi.org/10.26634/jcir.10.2.18907

Abstract

Every digital signal processing application performs multiplication operations. The addition and shift operations are part of multiplication operation. Many ideas have been created for computing systems with different design goals in terms of power, area, and speed. Typical architecture of these applications include digital signal processor (DSP), fast Fourier transform (FFT), and Multiply and Accumulate (MAC) unit. This paper offers a new way to increase the speed of DSP systems. This method uses four 2x2 LUT (look-up table) multipliers to demonstrate it at a 4x4 multiplier. The proposed multiplier was created using the Xilinx Vivado software and programmed in the Verilog HDL language. In addition, the delay, area, and power consumption of the proposed multiplier design differ from those of conventional multipliers. The simulation results show that, compared to typical methods, the operation consumes less power, reaching only 3.751 W compared to the conventional multiplier of 4.804 W, and shows lower latency.

References

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[10]. Lahari, P. L., Bharathi, M., & Shirur, Y. J. M. (2020b, July). High speed floating point multiply accumulate unit using offset binary coding. In 2020, 7th International Conference on Smart Structures and Systems (ICSSS), (pp. 1-5). IEEE. https://doi.org/10.1109/ICSSS49621.2020.9202333

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[14]. Murugesh, M. B., Nagaraj, S., Jayasree, J., & Reddy, G. V. K. (2020, July). Modified high speed 32-bit Vedic multiplier design and implementation. In 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC), (pp. 929-932). IEEE. https://doi.org/10.1109/ICESC48915.2020.9155882

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[16]. Prabhu, A. S., & Elakya, V. (2012, February). Design of modified low power booth multiplier. In 2012, International Conference on Computing, Communication and Applications, (pp. 1-6). IEEE. https://doi.org/10.1109/ICCCA.2012.6179166

[17]. Preetha, M., Kumar, N. A., Elavarasi, K., Vignesh, T., & Nagaraju, V. (2022). A hybrid clustering approach based Q-Leach in TDMA to optimize QOS-Parameters. Wireless Personal Communications, 123(2), 1169-1200. https://doi.org/10.1007/s11277-021-09175-8

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[20]. Ram, G. C., Lakshmanna, Y. R., Rani, D. S., & Sindhuri, K. B. (2016a, March). Area efficient modified Vedic multiplier. In 2016, International Conference on Circuit, Power and Computing Technologies (ICCPCT), (pp. 1-5). IEEE. https://doi.org/10.1109/ICCPCT.2016.7530294

[21]. Ram, G. C., Rani, D. S., Balasaikesava, R., & Sindhuri, K. B. (2016b, May). Design of delay efficient modified 16 bit Wallace multiplier. In 2016, IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), (pp. 1887-1891). IEEE. https://doi.org/10.1109/RTEICT.2016.7808163

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[23]. Swamy, K. A., Alex, Z. C., Ramachandran, P., Mathew, T. L., Sushma, C., & Padmaja, N. (2021, November). Real-time implementation of delay efficient DCT based hearing aid algorithm using TMS320C5505 DSP processor. In 2021, Innovations in Power and Advanced Computing Technologies (i-PACT), (pp. 1-8). IEEE. https://doi.org/10.1109/i-PACT52855.2021.9696632

[24]. Vardhan, A. S., Bharathi, M., & Padmaja, N. (2019). Convolution techniques using modified booth multiplication. i-manager's Journal on Digital Signal Processing, 7(2), 33-39. https://doi.org/10.26634/jdp.7.2.16697

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Research Paper

An Advanced MPPT Algorithm for PV Systems to Track GMPP under PSC Condition

A. Sireesha* , B. Mahesh Babu, K. Ravindra*

- Department of Electrical and Electronics Engineering, Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India.

Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Sireesha, A., Babu, B. M., and Ravindra, K. (2022). An Advanced MPPT Algorithm for PV Systems to Track GMPP under PSC Condition. i-manager’s Journal on Circuits and Systems, 10(2), 35-43. https://doi.org/10.26634/jcir.10.2.18857

Abstract

Growing demand for energy and concerns about environmental pollution has increased the use of renewable energy sources for electricity generation. Among all the renewable energy sources, solar energy is considered the most popular because of its huge benefits. This paper addresses two different problems with using photovoltaic (PV) systems in different applications. One of which is poor tracking performance, especially under partially shaded conditions (PSC). Therefore for global maximum power point (GMPP) tracking, a swarm intelligence-based maximum power point tracking (MPPT) method is used, which includes a particle swarm optimization (PSO) algorithm under the PSC, thereby improving the tracking efficiency of the PV system.

References

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[2]. Ahmed, J., & Salam, Z. (2017). An accurate method for MPPT to detect the partial shading occurrence in a PV system. IEEE Transactions on Industrial Informatics, 13(5), 2151-2161. https://doi.org/10.1109/TII.2017.2703079

[3]. Alik, R., & Jusoh, A. (2018). An enhanced P&O checking algorithm MPPT for high tracking efficiency of partially shaded PV module. Solar Energy, 163, 570-580. https://doi.org/10.1016/j.solener.2017.12.050

[4]. Alik, R., Jusoh, A., & Sutikno, T. (2015). A review on perturb and observe maximum power point tracking in photovoltaic system. TELKOMNIKA, 13(3), 745-751. http://doi.org/10.12928/telkomnika.v13i3.1439

[5]. Ellabban, O., Abu-Rub, H., & Blaabjerg, F. (2014). Renewable energy resources: Current status, future prospects and their enabling technology. Renewable and Sustainable Energy Reviews, 39, 748-764. https://doi.org/10.1016/j.rser.2014.07.113

[6]. Ishaque, K., & Salam, Z. (2013). A review of maximum power point tracking techniques of PV system for uniform insolation and partial shading condition. Renewable and Sustainable Energy Reviews, 19, 475-488. https://doi.org/10.1016/j.rser.2012.11.032

[7]. Jusoh, A. B., Mohammed, O. J. E. I., & Sutikno, T. (2015). Variable step size perturb and observe MPPT for PV solar applications. TELKOMNIKA, 13(1), 1-12. http:// doi.org/ 10.12928/telkomnika.v13i1.1180

[8]. Kazem, H. A., Chaichan, M. T., Alwaeli, A. H., & Mani, K. (2017). Effect of shadows on the performance of solar photovoltaic. In Mediterranean Green Buildings & Renewable Energy (pp. 379-385). Springer, Cham. https://doi.org/10.1007/978-3-319-30746-6_27

[9]. Koad, R. B., Zobaa, A. F., & El-Shahat, A. (2016). A novel MPPT algorithm based on particle swarm optimization for photovoltaic systems. IEEE Transactions on Sustainable Energy, 8(2), 468-476. https://doi.org/10.1109/TSTE.2016.2606421

[10]. Kollimalla, S. K., & Mishra, M. K. (2014). Variable perturbation size adaptive P&O MPPT algorithm for sudden changes in irradiance. IEEE Transactions on Sustainable Energy, 5(3), 718-728. https://doi.org/10.1109/TSTE.2014.2300162

[11]. Liu, Y. H., Huang, S. C., Huang, J. W., & Liang, W. C. (2012). A particle swarm optimization-based maximum power point tracking algorithm for PV systems operating under partially shaded conditions. IEEE Transactions on Energy Conversion, 27(4), 1027-1035. https://doi.org/10.1109/TEC.2012.2219533

[12]. Obukhov, S., Ibrahim, A., Diab, A. A. Z., Al-Sumaiti, A. S., & Aboelsaud, R. (2020). Optimal performance of dynamic particle swarm optimization based maximum power trackers for stand-alone PV system under partial shading conditions. IEEE Access, 8, 20770-20785. https://doi.org/10.1109/ACCESS.2020.2966430

[13]. Rezk, H., & Eltamaly, A. M. (2015). A comprehensive comparison of different MPPT techniques for photovoltaic systems. Solar Energy, 112, 1-11. https://doi.org/10.1016/j.solener.2014.11.010

[14]. Shadoul, M., Al Abri, R., Yousef, H., & Masoud, M. (2017, May). DC-DC boost converter controller design for PV applications. In 2017, 9th IEEE-GCC Conference and Exhibition (GCCCE) (pp. 1-6). IEEE. https://doi.org/10.1109/IEEEGCC.2017.8448164

[15]. Singh, O., & Gupta, S. K. (2018, March). A review on recent MPPT techniques for photovoltaic system. In 2018, IEEMA Engineer Infinite Conference (eTechNxT) (pp. 1-6). IEEE. https://doi.org/10.1109/ETECHNXT.2018.8385315

i-manager's Journal on Circuits and Systems (JCIR)

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Volume 10 Issue 2 July - December 2022

An Innovative FPGA-Based ADC/DAC Design using 1-Bit Adaptive-Delta Modulation

Akash Sardar* , Sayantan Dey**, Iti Saha Misra***

*-*** Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India.

Sardar, A., Dey, S., and Misra, I. S. (2022). An Innovative FPGA-Based ADC/DAC Design using 1-Bit Adaptive-Delta Modulation. i-manager’s Journal on Circuits and Systems, 10(2), 1-9. https://doi.org/10.26634/jcir.10.2.18902

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THD Analysis and Stability Enhancement of PID Controller in SRF-Based Shunt Active Filter under Different Design Criteria using GWO Technique

Nidhi Sahu* , Sandeep Sahu**, Pushpa Sahu***

*-** Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India. *** Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Durg, Chhattisgarh, India.

Sahu, N., Sahu, S., and Sahu, P. (2022). THD Analysis and Stability Enhancement of PID Controller in SRF-Based Shunt Active Filter under Different Design Criteria using GWO Technique. i-manager’s Journal on Circuits and Systems, 10(2), 19-27. https://doi.org/10.26634/jcir.10.2.18912

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Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop

Varun* , Bal Krishan**, Rohit Tripathi***

*-*** Department of Electronics Engineering, YMCA University of Science and Technology, Faridabad, Haryana, India.

Varun, Krishan, B., and Tripathi, R. (2022). Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop. i-manager’s Journal on Circuits and Systems, 10(2), 10-18. https://doi.org/10.26634/jcir.10.2.18978

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A Novel Multiplication Design Based on LUT Method

Tharun Kumar Reddy M.* , M. Bharathi**, N. Padmaja***, B. Ashreetha****

*-**** Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.

Reddy, M. T. K., Bharathi, M., Padmaja, N., and Ashreetha, B. (2022). A Novel Multiplication Design Based on LUT Method. i-manager’s Journal on Circuits and Systems, 10(2), 28-34. https://doi.org/10.26634/jcir.10.2.18907

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An Advanced MPPT Algorithm for PV Systems to Track GMPP under PSC Condition

A. Sireesha* , B. Mahesh Babu**, K. Ravindra***

*-** Department of Electrical and Electronics Engineering, Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India. *** Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Sireesha, A., Babu, B. M., and Ravindra, K. (2022). An Advanced MPPT Algorithm for PV Systems to Track GMPP under PSC Condition. i-manager’s Journal on Circuits and Systems, 10(2), 35-43. https://doi.org/10.26634/jcir.10.2.18857

Abstract

References

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Akash Sardar* , Sayantan Dey, Iti Saha Misra*

Nidhi Sahu* , Sandeep Sahu, Pushpa Sahu*

- Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India.

Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Durg, Chhattisgarh, India.

Varun* , Bal Krishan, Rohit Tripathi*

Tharun Kumar Reddy M.* , M. Bharathi, N. Padmaja*, B. Ashreetha****

A. Sireesha* , B. Mahesh Babu, K. Ravindra*

- Department of Electrical and Electronics Engineering, Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India.

Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.