i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 12 Issue 1

Unified Power Quality Conditioner Research Study on STEADY - STATE POWER FLOW

Most Cited

Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline

Volume 10 Issue 1 January - June 2022

Research Paper

Development of a General Purpose First-In-First-Out (FIFO) Core

Marcus Lloyde George* , Nora Innocent-George**

* Department of Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad and Tobago.

** Department of Science and Agriculture, University of the West Indies, St. Augustine, Trinidad and Tobago.

George, M. L., and Innocent-George, N. (2022). Development of a General Purpose First-In-First-Out (FIFO) Core. i-manager’s Journal on Circuits and Systems, 10(1), 1-14. https://doi.org/10.26634/jcir.10.1.18663

Abstract

First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.

References

[1]. Abdelhadi, A. M. S. (2020). Synthesizable synchronization FIFOs utilizing the asynchronous pulsebased handshake protocol. In 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 1-7. https://doi.org/10.1109/NorCAS51424.2020.9265139

[2]. Abdel hafeez, S., & Gordon Ross, A. (2021). Reconfigurable FIFO memory circuit for synchronous and asynchronous communication. International Journal of Circuit Theory and Applications, 49(4), 938-952. https://doi.org/10.1002/cta.2921

[3]. Ashour, H. (2015). Design, simulation and realization of a parametrizable, configurable and modular asynchronous FIFO. In 2015 Science and Information Conference (SAI), 1391-1395. https://doi.org/10.1109/SAI.2015.7237325

[4]. Bhatnagar, V., Kumar, S., Pandey, M. K., & Pandey, S. (2020). Design and implementation of an efficient buffer management system for network on chip routers. In 2020 9th International Conference System Modeling and Advancement in Research Trends (SMART), 314-317. https://doi.org/10.1109/SMART50582.2020.9337128

[5]. Drozdek, A. (2013). Data Structures and Algorithms in C++. Cengage learning.

[6]. Gordon-Ross, A., Abdel-Hafeez, S., & Alsafrjalni, M. H. (2019). A one-cycle FIFO buffer for memor y management units in manycore systems. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 265-270. https://doi.org/10.1109/ISVLSI.2019.00056

[7]. Hsu, W. S., Huang, P. T., Wu, S. L., Chuang, C. T., Hwang, W., Tu, M. H., & Yin, M. Y. (2016). 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms. In 2016 International Symposium on VLSI Design, Automation and Test (VLSIDAT), 1-4. https://doi.org/10.1109/VLSI-DAT.2016.7482551

[8]. Mansi, J., & Kapoor, S. (2014). A synthesizable RTL design of asynchronous FIFO interfaced with SRAM. International Journal of Computer Science and Information Technologies, 5(2), 2033-2037

[9]. Perry, D. (1998). VHDL, 3rd edition. McGraw-Hill, New York.

[10]. Rizvi, N. Z., Arora, R., & Agrawal, N. (2015). Implementation and verification of synchronous FIFO using system Verilog verification methodology. Journal of Communications Technology, Electronics and Computer Science, 2, 18-23. 10.22385/jctecs.v2i0.19

[11]. Shilpi, M. (2016). Design of RTL synthesizable 32-bit FIFO memory. International Journal of Engineering Research and Technology (IJERT), 5(11), 591-593

[12]. Windmann, S., & Jasperneite, J. (2015). An FPGA based FIFO with efficient memory management. In 2015 IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA), 1-4. https://doi.org/10.1109/ETFA.2015.7301585

[13]. Zhang, X., Wang, J., Wang, Y., Chen, D., & Lai, J. (2012). BRAM-based asynchronous FIFO in FPGA with optimized cycle latency. In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 1-3. https://doi.org/10.1109/ICSICT.2012.6467891

[14]. Zhang, Y., Yi, C., Wang, J., & Zhang, J. (2011). Asynchronous FIFO implementation using FPGA. In Proceedings of 2011 International Conference on Electronics and Optoelectronics, 3, (pp. 207). https://doi.org/10.1109/ICEOE.2011.6013339

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Research Paper

Performance Analysis of Shunt Active Filter Based on SRF Theory using Metaheuristic Optimization Technique for Nonlinear Loads

Nidhi Sahu* , Sandeep Sahu**

*-** Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India.

Sahu, N., and Sahu, S. (2022). Performance Analysis of Shunt Active Filter Based on SRF Theory using Metaheuristic Optimization Technique for Nonlinear Loads. i-manager’s Journal on Circuits and Systems, 10(1), 15-24. https://doi.org/10.26634/jcir.10.1.18845

Abstract

Power electronic devices play a vital role in manufacturing process, research and development because it delivers high efficiency, low cost, rapid operation, and optimal size. In recent years, power electronic devices have become widely employed in a variety of fields. Harmonics have a substantial impact on power systems and the main sources of harmonics are nonlinear loads and energy conversion devices such as static converters, choppers, cyclo-converters, battery charging systems, and heating elements, among others. To reduce harmonics, different filtration technologies are available, with the shunt active power filter being one of the most significant and effective. The performance of a shunt active power filter based on synchronous reference frame theory is explored and the efficiency is improved utilising the satin bower bird optimization approach.

References

[1]. Abdollahzadeh, B., Gharehchopogh, F. S., & Mirjalili, S. (2021). African vultures optimization algorithm: A new nature-inspired metaheuristic algorithm for global optimization problems. Computers & Industrial Engineering, 158, (pp. 107408).

[2]. Benedict, E., Collins, T., Gotham, D., Hoffman, S., Karipides, D., Pekarek, S., & Ramabhadran, R. (1992). Losses in electric power systems. ECE Technical Reports.

[3]. Davidson, C. C., & Préville, G. D. (2009). The future of high power electronics in transmission and distribution power systems. In 2009 13th European Conference on Power Electronics and Applications, 1-14.

[4]. Fan, J., Li, Y., & Wang, T. (2021). An improved African vultures optimization algorithm based on tent chaotic mapping and time-varying mechanism. Plos One, 16(11), (pp. 0260725). https://doi.org/10.1371/journal.pone.0260725

[5]. Guru, R. P., & Vaithianathan, V. (2020). An efficient VLSI circuit partitioning algorithm based on satin bowerbird optimization (SBO). Journal of Computational Electronics, 19(3), 1232-1248. https://doi.org/10.1007/s10825-020-01491-9

[6]. Halpin, S. M. (2005). Comparison of IEEE and IEC harmonic standards. In IEEE Power Engineering Society General Meeting, 2005, 2214-2216. https://doi.org/10.1109/PES.2005.1489688

[7]. Jou, H. L., Wu, J. C., Chang, Y. J., & Feng, Y. T. (2005). A novel active power filter for harmonic suppression. IEEE Transactions on Power Delivery, 20(2), 1507-1513. https://doi.org/10.1109/TPWRD.2004.841305

[8]. Kabir, M. A., & Mahbub, U. (2011). Synchronous detection and digital control of shunt active power filter in power quality improvement. In 2011 IEEE Power and Energy Conference at Illinois, 1-5. https://doi.org/10.1109/PECI.2011.5740499

[9]. Kusko, A., & Thompson, T. M. (2007). Power quality in electrical systems. McGraw-Hill Education, 1-14.

[10]. Luo, F. L., & Ye, H. (2017). Power electronics: advanced conversion technologies. CRC press, Boca Raton, (pp. 735). https://doi.org/10.1201/9781315186276

[11]. Martins, F. G. (2005). Tuning PID controllers using the ITAE criterion. International Journal of Engineering Education, 21(5), 867.

[12]. Moosavi, S. H. S., & Bardsiri, V. K. (2017). Satin bowerbird optimizer: A new optimization algorithm to optimize ANFIS for software development effort estimation. Engineering Applications of Artificial Intelligence, 60, 1-15. https://doi.org/10.1016/j.engappai.2017.01.006

[13]. Panchbhai, A., Prajapati, N., & Parmar, S. (2017). Comparative study of reference current generation for shunt active power filter. In 2017 International Conference on Power and Embedded Drive Control (ICPEDC), 381-386. https://doi.org/10.1109/ICPEDC.2017.8081119

[14]. Sannino, A., Svensson, J., & Larsson, T. (2003). Powerelectronic solutions to power quality problems. Electric Power Systems Research, 66(1), 71-82. https://doi.org/10.1016/S0378-7796(03)00073-7

[15]. Sira-Ramirez, H. (1991). Nonlinear P-I controller design for switchmode DC-to-DC power converters. IEEE Transactions on Circuits and Systems, 38(4), 410-417. https://doi.org/10.1109/31.75397

[16]. Svensson, J., Jones, P., & Halvarsson, P. (2006). Improved power system stability and reliability using innovative energy storage technologies. In The 8th IEE International Conference on AC and DC Power Transmission, 220-224. https://doi.org/10.1049/cp:20060045

[17]. Wang, Y. G., & Shao, H. H. (2000). Optimal tuning for PI controller. Automatica, 36(1), 147-152. https://doi.org/10.1016/S0005-1098(99)00130-2

[18]. Zaveri, N., Mehta, A., & Chudasama, A. (2009). Performance analysis of various SRF methods in three phase shunt active filters. In 2009 International Conference on Industrial and Information Systems (ICIIS), 442-447. https://doi.org/10.1109/ICIINFS.2009.5429819

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Research Paper

Low Power SRAM Cell Design with Power Gating Technique

V. Seetha*

Department of Electronics and Communication Engineering, Meenakshi Ramaswamy Engineering College, Ariyalur, Tamil Nadu, India.

Seetha, V. (2022). Low Power SRAM Cell Design with Power Gating Technique. i-manager’s Journal on Circuits and Systems, 10(1), 25-34. https://doi.org/10.26634/jcir.10.1.18569

Abstract

The power consumption of Static Random-Access Memory (SRAM) cell is considered as a major factor in modern technologies due to voltage scaling. The existing SRAM cell design of consumes more power at higher frequencies. In the proposed work, power reduction is achieved in various radiation-hardened SRAM cell designs which is based on power gating technique. Hence, the power gated voltage (VDD) design technique is employed to reduce power consumption.

References

[1]. Peng, C., Huang, J., Liu, C., Zhao, Q., Xiao, S., Wu, X., ..., & Zeng, X. (2018). Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 407-415. https://doi.org/10.1109/TVLSI.2018.2879341

[2]. Han, Y., Cheng, X., Han, J., & Zeng, X. (2020). Radiation-hardened 0.3–0.9-V voltage-scalable 14T SRAM and peripheral circuit in 28-nm technology for space applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(4), 1089-1093. https://doi.org/10.1109/TVLSI.2019.2961736

[3]. Atias, L., Teman, A., & Fish, A. (2014). Single event upset mitigation in low power SRAM design. In 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), 1-5. https://doi.org/10.1109/EEEI.2014.7005796

[4]. Gupta, V., & Anis, M. (2010). Statistical design of the 6T SRAM bit cell. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), 93-104. https://doi.org/10.1109/TCSI.2009.2016633

[5]. Gavaskar, K., Vidyaa T. E., Suresh S., & Thangaraj N. (2019). Design and comparative analysis of SRAM with performance optimization using MTCMOS technique for high speed computation. International Journal of Computer Applications, 182(36), 1-5. https://doi.org/10.5120/ijca2019918350

[6]. Raghuram, C. N., Gupta, B., & Kaushal, G. (2020). Double node upset tolerant RHBD15T SRAM cell design for space applications. IEEE Transactions on Device and Materials Reliability, 20(1), 181-190. https://doi.org/10.1109/TDMR.2020.2970089

[7]. Kumar, H., & Saun, S. (2019). Power gated technique to improve design metrics of 6T SRAM memory cell for low power applications. ICTACT Journal on Microelectronics, 5(3), 815-819. https://doi.org/10.21917/ijme.2019.0140

[8]. Anandani, D., Kumar, A., & Bhaaskaran, V. K. (2015). Gating techniques for 6T SRAM cell using different modes of FinFET. In 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 483-487. https://doi.org/10.1109/ICACCI.2015.7275655

[9]. Saxena, S., & Mehra, R. (2016). High performance and low power SRAM cell design using power gating technique. International Journal of Electrical and Electronic Engineering and Telecommunications, 5(3), 35-47.

[10]. Guo, J., Xiao, L., & Mao, Z. (2014). Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 1994-2001. https://doi.org/10.1109/TCSI.2014.2304658

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Research Paper

Open Circuit Fault-Tolerant Operation of 3-Φ Multilevel Inverter

Sunil Manjhi* , Rajkumar Jhapte**

* Department of Electrical Engineering, Shri Shankaracharya Group of Institution, Junwani, Chhattisgarh, India.

** Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Junwani, Bhilai, Chhattisgarh, India.

Manjhi, S. and Jhapte, R. (2022). Open Circuit Fault-Tolerant Operation of 3-Φ Multilevel Inverter. i-manager’s Journal on Circuits and Systems, 10(1), 35-42. https://doi.org/10.26634/jcir.10.1.18816

Abstract

A modified Fault-Tolerant (FT) structure is presented for the five-level Multi-Level Inverter (MLI) in this research work. A self capacitor voltage balancing control regulates the voltage across the capacitor by a half magnitude of the DC source value to produce a five-level output voltage waveform. Furthermore, the self capacitor voltage balancing control reduces complexity and enhances system reliability. A possible Open Circuit (OC) fault in the switches of the proposed structure is further analyzed. On the basis of a comparative analysis between the five-level MLI and the proposed faulttolerant structure, this structure is presented. When compared with the most recent FT topologies, it contains fewer devices. MATLAB/Simulink are used to study the proposed single-phase and three-phase FT structures under pre-fault, fault and post-fault operation.

References

[1]. Bana, P. R., Panda, K. P., Naayagi, R. T., Siano, P., & Panda, G. (2019). Recently developed reduced switch multilevel inverter for renewable energy integration and drives application: topologies, comprehensive analysis and comparative evaluation. IEEE Access, 7, 54888- 54909.https://doi.org/10.1109/ACCESS.2019.2913447

[2]. Chen, A., Hu, L., Chen, L., Deng, Y., & He, X. (2005). A multilevel converter topology with fault-tolerant ability. IEEE Transactions on Power Electronics, 20(2), 405-415. https://doi.org/10.1109/TPEL.2004.842983

[3]. Dewangan, N. K., Gupta, S., & Gupta, K. K. (2019). Approach to synthesis of fault tolerant reduced device count multilevel inverters (FT RDC MLIs). IET Power Electronics, 12(3), 476-482. https://doi.org/10.1049/ietpel.2018.5176

[4]. Dewangan, N. K., Tailor, T. K., Agrawal, R., Bhatnagar, P., & Gupta, K. K. (2021). A multilevel inverter structure with open circuit fault-tolerant capability. Electrical Engineering, 103(3), 1613-1628. https://doi.org/10.1007/s00202-020-01149-6

[5]. Gautam, S. P., Gupta, S., & Kumar, L. (2017). Reliability improvement of transistor clamped H bridge based cascaded multilevel inverter. IET Power Electronics, 10(7), 770-781. https://doi.org/10.1049/iet-pel.2016.0574

[6]. Gupta, K. K., Ranjan, A., Bhatnagar, P., Sahu, L. K., & Jain, S. (2015). Multilevel inverter topologies with reduced device count: A review. IEEE Transactions on Power Electronics, 31(1), 135-151. https://doi.org/10.1109/TPEL.2015.2405012

[7]. Metri, J. I., Vahedi, H., Kanaan, H. Y., & Al-Haddad, K. (2016). Real-time implementation of model-predictive control on seven-level packed U-cell inverter. IEEE Transactions on Industrial Electronics, 63(7), 4180-4186. https://doi.org/10.1109/TIE.2016.2542133

[8]. Nicolas-Apruzzese, J., Busquets-Monge, S., Bordonau, J., Alepuz, S., & Calle-Prado, A. (2012). Analysis of the fault-tolerance capacity of the multilevel active-clamped converter. IEEE Transactions on Industrial Electronics, 60(11), 4773-4783. https://doi.org/10.1109/TIE.2012.2222856

[9]. Ounejjar, Y., & Al-Haddad, K. (2010). A novel six-band hysteresis control of the packed U cells seven-level converter. In 2010 IEEE International Symposium on Industrial Electronics, 3199-3204. https://doi.org/10.1109/ISIE.2010.5637579

[10]. Ounejjar, Y., Al-Haddad, K., & Dessaint, L. A. (2011). A novel six-band hysteresis control for the packed U cells seven-level converter: Experimental validation. IEEE Transactions on Industrial Electronics, 59(10), 3808-3816. https://doi.org/10.1109/TIE.2011.2161059

[11]. Ounejjar, Y., Al-Haddad, K., & Gregoire, L. A. (2010). Packed U cells multilevel converter topology: theoretical study and experimental validation. IEEE Transactions on Industrial Electronics, 58(4), 1294-1306. https://doi.org/10.1109/TIE.2010.2050412

[12]. Rao, A. M., & Sivakumar, K. (2015). A fault-tolerant single-phase five-level inverter for grid-independent PV systems. IEEE Transactions on Industrial Electronics, 62(12), 7569-7577. https://doi.org/10.1109/TIE.2015.2455523

[13]. Rodriguez, J., Bernet, S., Steimer, P. K., & Lizama, I. E. (2009). A survey on neutral-point-clamped inverters. IEEE Transactions on Industrial Electronics, 57(7), 2219-2230. https://doi.org/10.1109/TIE.2009.2032430

[14]. Sebaaly, F., Sharifzadeh, M., Kanaan, H. Y., & Al- Haddad, K. (2021). Multilevel switching-mode operation of finite-set model predictive control for grid-connected packed e-cell inverter. IEEE Transactions on Industrial Electronics, 68(8), 6992-7001. https://doi.org/10.1109/TIE.2020.3003627

[15]. Sheir, A., Orabi, M., Ahmed, M. E., Iqbal, A., & Youssef, M. (2014). A high efficiency single-phase multilevel packed U cell inverter for photovoltaic applications. In 2014 IEEE 36th International Telecommunications Energy Conference (INTELEC), 1-6. https://doi.org/10.1109/INTLEC.2014.6972164

[16]. Trabelsi, M., Bayhan, S., Ghazi, K. A., Abu-Rub, H., & Ben-Brahim, L. (2016). Finite-control-set model predictive control for grid-connected packed-U-cells multilevel inverter. IEEE Transactions on Industrial Electronics, 63(11), 7286-7295. https://doi.org/10.1109/TIE.2016.2558142

[17]. Vahedi, H., & Al-Haddad, K. (2016). Real-time implementation of a seven-level packed U-cell inverter with a low-switching-frequency voltage regulator. IEEE Transactions on Power Electronics, 31(8), 5967-5973. https://doi.org/10.1109/TPEL.2015.2490221

[18]. Vahedi, H., Labbé, P. A., & Al-Haddad, K. (2015). Sensor-less five-level packed U-cell (PUC5) inverter operating in stand-alone and grid-connected modes. IEEE Transactions on Industrial Informatics, 12(1), 361-370. https://doi.org/10.1109/TII.2015.2491260

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Research Paper

Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology

G. Appala Naidu*

Department of Electronics and Communication Engineering, JNTU-GV, College of Engineering Vizianagaram, Andhra Pradesh, India.

Naidu, G. A. (2022). Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology. i-manager’s Journal on Circuits and Systems, 10(1), 43-48. https://doi.org/10.26634/jcir.10.1.18616

Abstract

In this paper a low offset voltage; low power and high gain second stage op-amp of differential amplifier along with common source amplifier with compensated capacitor is proposed. The mathematical analysis of two-stage op-amp is elaborated and this work is compared with exiting similar work. The experimental work carried in CADENCE Virtuoso with 0 gpdk090 process technology is used to obtain 60.994 of Phase Margin, 61 dB DC gain and Offset voltage is 2mV. The M/L ratios are selected accordingly where supply voltage and load voltage are fixed at 1.8V and 12pF respectively. The parametric analysis helps, where the values are fixed to get better response.

References

[1]. Abdullah-Al-Kaiser, M., & Jarin, I. (2017). High gain low offset faster two stage CMOS op-amp and effects of aspect ratios on gain. In 2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE), 253-256. https://doi.org/10.1109/WIECON-ECE.2017.8468913

[2]. Allen, P. E., & Holmberg, D. R. (2002). CMOS Analog Circuit Design, 2nd Edition. Oxford University Press, New York.

[3]. Baruah, R. K. (2010). Design of a low power, low voltage CMOS op-amp. International Journal of VLSI Design and Communication System (VLSICS), l (1). https://doi.org/10.5121/vlsic.2010.1101

[4]. Chowdhury, S. A., Bose, O. P., & Hossain, Q. D. (2018). Design of a Two Stage CMOS Operational Amplifier in 100nm Technology with Low Offset Voltage. In 2018 International Conference on Innovations in Science, Engineering and Technology (ICISET), 56-59. https://doi.org/10.1109/ICISET.2018.8745659

[5]. Davidovic, M. D. (1999). A simple proof of Miller's theorem. IEEE Transactions on Education, 42(2), 154-155. http:/doi.org/10.1109/13.762956

[6]. Enz, C. C., & Temes, G. C. (1996). Circuit techniques for reducing the effects of op-amp imperfections: Auto zeroing, correlated double sampling, and chopper stabilization. Proceedings of the IEEE, 84(11), 1584-1614. http:/doi.org/10.1109/5.542410

[7]. Lu, C. W. (2007). An offset cancellation technique for two-stage CMOS operational amplifiers. In 2007 IEEE International Conference on Integrated Circuit Design and Technology, 1-3. http:/doi.org/10.1109/ICICDT.2007.4299561

[8]. Millman, J., & Halkias, C. C. (1972). Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill, New York.

[9]. Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. McGraw-Hill.

[10]. Sedra, A. S., & Smith, K. C. (2004). Microelectronic Circuits. Oxford University Press, New York.

[11]. Shankar, C., & Kaur, M. (2010). Stability and bandwidth enhancement of two stage op-amp using negative capacitance generation. International Journal of Micro and Nano Electronics, Circuits and Systems, 2(2), 113-118.

[12]. Witte, F., Makinwa, K. A. A., & Huijsing, J. (2009). Dynamic Offset Compensated CMOS Amplifiers. Springer, New York, (6-37).

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 12 Issue 1

Most Read

Most Cited

Volume 10 Issue 1 January - June 2022

Development of a General Purpose First-In-First-Out (FIFO) Core

Marcus Lloyde George* , Nora Innocent-George**

* Department of Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad and Tobago. ** Department of Science and Agriculture, University of the West Indies, St. Augustine, Trinidad and Tobago.

George, M. L., and Innocent-George, N. (2022). Development of a General Purpose First-In-First-Out (FIFO) Core. i-manager’s Journal on Circuits and Systems, 10(1), 1-14. https://doi.org/10.26634/jcir.10.1.18663

Abstract

References

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Performance Analysis of Shunt Active Filter Based on SRF Theory using Metaheuristic Optimization Technique for Nonlinear Loads

Nidhi Sahu* , Sandeep Sahu**

*-** Department of Electrical and Electronics Engineering, Chhatrapati Shivaji Institute of Technology, Durg, Chhattisgarh, India.

Sahu, N., and Sahu, S. (2022). Performance Analysis of Shunt Active Filter Based on SRF Theory using Metaheuristic Optimization Technique for Nonlinear Loads. i-manager’s Journal on Circuits and Systems, 10(1), 15-24. https://doi.org/10.26634/jcir.10.1.18845

Abstract

References

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Low Power SRAM Cell Design with Power Gating Technique

V. Seetha*

Department of Electronics and Communication Engineering, Meenakshi Ramaswamy Engineering College, Ariyalur, Tamil Nadu, India.

Seetha, V. (2022). Low Power SRAM Cell Design with Power Gating Technique. i-manager’s Journal on Circuits and Systems, 10(1), 25-34. https://doi.org/10.26634/jcir.10.1.18569

Abstract

References

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Open Circuit Fault-Tolerant Operation of 3-Φ Multilevel Inverter

Sunil Manjhi* , Rajkumar Jhapte**

* Department of Electrical Engineering, Shri Shankaracharya Group of Institution, Junwani, Chhattisgarh, India. ** Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Junwani, Bhilai, Chhattisgarh, India.

Manjhi, S. and Jhapte, R. (2022). Open Circuit Fault-Tolerant Operation of 3-Φ Multilevel Inverter. i-manager’s Journal on Circuits and Systems, 10(1), 35-42. https://doi.org/10.26634/jcir.10.1.18816

Abstract

References

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Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology

G. Appala Naidu*

Department of Electronics and Communication Engineering, JNTU-GV, College of Engineering Vizianagaram, Andhra Pradesh, India.

Naidu, G. A. (2022). Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology. i-manager’s Journal on Circuits and Systems, 10(1), 43-48. https://doi.org/10.26634/jcir.10.1.18616

Abstract

References

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* Department of Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad and Tobago.

** Department of Science and Agriculture, University of the West Indies, St. Augustine, Trinidad and Tobago.

* Department of Electrical Engineering, Shri Shankaracharya Group of Institution, Junwani, Chhattisgarh, India.

** Department of Electrical and Electronics Engineering, Shri Shankaracharya Technical Campus, Junwani, Bhilai, Chhattisgarh, India.