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i-manager's Journal on Electrical Engineering (JEE)

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PV-grid Performance improvement through Integrated Intelligent Water Drop Optimization with Neural Network for Maximum Power Point Tracking
A Digital Healthcare Monitoring System with Real-Time Analysis
Advancements in Smart Meter Design and Integration for Enhanced Energy Management and Efficiency
Electric Vehicles in Modern Transportation: Environmental Impacts, Configurations, and Future Trends – A Review
GTO Technique Based Hybrid Power System Controller Design

Most Cited

Volume 1 Issue 4 April - June 2008

Article

The Modeling of Analogue Systems through an Object-Oriented Design Method

Tom Page*

* Lecturer, Department of Design and Technology, Loughborough University Loughborough, Lelcs, UK.

Tom Page (2008). The Modeling of Analogue Systems through an Object-Oriented Design Method. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 1-8. https://doi.org/10.26634/jee.1.4.368

Abstract

This paper reports on work done in extending an object-oriented co-design method to include analogue hardware. This method is based on the development of a set of dynamic simulation models. These models support the development of the system by providing, initially, an uncommitted, behavioural model, which has evolved into a committed model that specifies the implementation of this system. During the commitment process, parts of the uncommitted logical model are committed to a particular implementation technology. Thus the notation used, and the simulation strategy, must support the evaluation of subsystems implemented as software, digital or analogue hardware. This paper focuses on the requirements for modeling hardware a hybrid system model; i.e.

• A notation that supports the representation evaluation of analogue hardware.

• The simulation strategy required to incorporate models of analogue subsystems.

• The ability to carry forward information contained in the models to implementation.

This presents a small, yet pertinent, example of such a model. This is a wholly analogue model of a Carver-Mead type neural system.

References

[1] . Booch, G. (1991), Object-Oriented Design, Benjamin/Cummings: Redwood CityCa.

[2] . Bourbakis , N.G., Mortazavi, M. (2005), A VLSI Design Design-Synthesis Methodology at the Transistor Layout Level, Journal of Integrated Design & Process Science, Vol.9No.3, pp.63-85.

[3] . Edwards, M.D. (1992), Automatic Logic Synthesis Techniques for Digital Systems, McGraw 11111, New York NY.

[4] . Evans D.G. and D. Morris. (1993), 'Applying Modeling To Embedded Computer Systems Designed, in CoDesign : Computer Aided Software Hardware Engineering 6, IEEE Press.

[5] . Kilbane, D. (2004), Carver Mead: A Trip Through Four Eras of Innovation. Electronic Design. New York. Vol. 52; No. 20, pp.96-98.

[6] . Labrak, L., Tixier, T., Fellah, Y. and Abouchi, N. (2007),A New Approach for Automated Analog Design Optimisation. Proceedings of the 11th International conference on circuits; Circuits theory and applications: Greece 2007; July, pp. 17-21.

[7] . Roca, M., Isern, E., Picos, R., Bota, S., Suenaga, K. and Garcia-Moreno, E. (2007), Circuit Theory & Design - Accuracy evaluation in parameter prediction of analogue circuits using nonlinear oscillation methods. Electronics letters. Vol. 43, no. 9, pp.494.

[8] . Seon, J.K. (2008), Design and application of precise analog computational circuits. Analog Integrated Circuits and Signal ProcessingVo\.54, no. I pp. 55-66.

[9] . Thompson, M. (2006), Intuitive Analog Circuit Design. Elsevier, ISBN: 9780080478753.

[10] . Tuite, D. (2008), Analog Overview Apps Drive Innovation, But The Design Environment Is Changing. Electronic Design -New York. Vol. 56; No. 1, pp.25.

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Research Paper

A 65µA 8MHz Integrated Oscillator with LDO Regulator Supply for Low-Power Handheld SoC Applications

Jacob Day* , Paul Vulpoiu, Jeffery Julich*, Donald Lie****

Department of Electrical and Computer Engg.,Texas Tech,University,Lubbock,TX,U.S.A

,,Texas Instruments Inc.Dallas,TX,U.S.A.

****Associate Professor,Department of Electrical and Computer Engg.,Texas Tech,University,Lubbock,TX,U.S.A

Jacob Day, Paul Vulpoiu , Jeffery Julich and Donald Lie (2008). A 65µA 8MHz Integrated Oscillator with LDO Regulator Supply for Low-Power Handheld SoC Applications. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 9-14. https://doi.org/10.26634/jee.1.4.369

Abstract

This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage do not affect the oscillator. The circuits have been designed and taped out and the measured results are closed to the SPICE simulated values. The oscillator has low power consumption of 165 µW which is very attractive for a general handheld device that is operated off of a battery.

References

[1] . A. Hastings, The Art of Analog Layout Prentice Hall (2005).

[2] . A. Aloisio, R Branchini, F. Cevenini, V. Izzo, S. Loffredo and R. Lomoro, "Signal Integrity and Timing Issues of VME64x Double Edge Cycles", IEEE Transactions on Nuclear Science, pp. 520-525 (2006).

[3] . C.W. Lin and Y.J. Liu, "A Power Efficient and Fast Transient Response Low Drop-Out Regulator in Standard CMOS Process", IEEE Inti Symp. VLSI Design Automation and Test (VLDI-DAT], pp. 1 -4, Hsinchu, Taiwan, (2006).

[4] . C.K. Chava and J. Si Iva-Martinez, "A Frequency Compensation Scheme for LDO Voltage Regulators", IEEE Transactions on Circuits and Systems Vol. 5b pp. 1041-1050(2004).

[5] . G.A. Rincon-Mora and RE. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE Journal of Solid-State Circuits, Vol. 33, pp. 36-44 (1998).

[6] . A.L.V. Boas, J.B.D. Soldera, A. Olmos, "A 1.8 V supply multi-frequency digitally trimmable on-chip 1C oscillator with low-voltage detection capability", IEEE 17th Symp. on Integrated Circuits and Systems Design [SBCCI], pp. 44-48, Brazil, Sept. 7-11, (2004).

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Research Paper

Behavior Modeling and Comparison of Envelope Tracking vs Envelope-Elimination-and-Restoration for Class E SiGe PA Linearization

Yan Li* , Jerry Lopez, Donald Lie*

Department of Electrical and Computer Engineering, TexasTech. University, Lubbock, TX, U.S.A.

Department of Electrical and Computer Engineering, TexasTech. University, Lubbock, TX, U.S.A.

Associate Professor, Department of Electrical and Computer Engineering, Texas Tech. University, Lubbock, TX, U.S.A.

Yan Li, Jerry Lopez and Donald Lie(2008). Behavior Modeling and Comparison of Envelope Tracking vs Envelope-Elimination-and-Restoration for Class E SiGe PA Linearization. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 15-21. https://doi.org/10.26634/jee.1.4.371

Abstract

A modified bias-dependent Cann’s model and performed IC design and hardware experiments to study the linearization of a highly-efficient monolithic quasi-class E SiGe power amplifier (PA) IC using both Envelope-Tracking (ET) and Envelope-Elimination-and-Restoration (EER) techniques. Our PA behavior model fits the measured SiGe PA IC data very well across a wide range of bias and supply voltages. Both measurement and simulations show that the ET-linearized PA system is significantly less sensitive to the timing misalignment between the amplitude and the RF signal path than the EER-linearized PA system. Our experimental results also prove that ET successfully linearized the SiGe PA to pass the stringent EDGE transmit mask at 900MHz, while EER could not. Simulations based on our PA behavior model predict that the optimal timing alignment for ET linearization can be achieved at PA base bias voltage Vbb=0.55-0.6V, which is consistent with our measurement results as well.

References

[l]. N.O. Sokal and A.D. Sokal, "Class E-a new Class of high efficiency tuned single-ended switching power amplifiers", IEEE J. Solid-State Circuits, vol. 10, no, 3, pp. 168-176, June (1975).

[2] . F. H. Raab, "Idealized Operation of the Class E Tuned Power Amplifier," IEEE Trans. Circuits Syst., vol. 24, no. 12, pp. 725-735, Dec. (1977),

[3] . K. Tsai and RR. Gray, "A 1.9-GHz, 1 -W CMOS Class-E Power Amplifier for Wireless Communications," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 962-970, July (1999),

[4] . C. Yoo and Q. Huang, "A common-gate switched 0.9-W Class-E power amplifier with 41% PAE In 0.25-um CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 823-830, May (2001).

[5] . Y. Tan, M. Kumar, J.K.O. Sin, L. Shi and J. Lau, “A 900- MHz fully integrated SOI power amplifier for single chip wireless transceiver applications," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1481 -1486, (2000).

[6] . K.-W. Ho and H.C. Luong, "A 1-V CMOS power amplifier for Bluetooth applications," IEEE Trans. Circuits and Systems II, Analog Digit. Signal Process., vol. 50, no. 8, pp. 445-449, Aug. (2003).

[7] . A. Scuderl, L. La Pag I la, F. Carrara and G. Palmlsano, "A VSWR-Protected Silicon bipolar RF power amplifier with soft-slope power control", IEEE J. Solid-State Circuits, vol. 40, no, 3, pp. 611 -621, May (2005).

[8] . A. Mazzanti, L. Larcher, R. Brama and F. Svelto, "Analysis of reliability and power efficiency in cascode Class-E PAs", IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1222-1229, May(2006).

[9]. N.O. Sokal, "Class-E switching-mode high-effiicency tuned RF/MIcrowave power amplifier: Improved design equations", IEEEMTT-S, pp. 779-782, (2000

[10]. D.Y.C. Lie, R Lee, J.D. Popp, J.F. Rowland, H.H. Ng and A.H. Yang, "The Limitations in Applying Analytic Design Equations for Optimal Class E RF Power Amplifiers Design", Proc. Tech. Dig., IEEE Inf I Symp. on VLSI Design, Automation, and Test(VLSI-TSA-DAT), Hsin-Chu, Taiwan, pp. 161-164, Apr. (2005).

[11 ]. R. Negra and W. Bachtold, "Lumped-element load- network design for class-E power amplifiers," IEEE Trans. Microwave Theory and Techniques, vol. 54, no. 6, pp. 2684-2690, June (2006).

[12] , F. Wang, A.H. Yang, D.F. Kimball, L.E. Larson and RM. Asbeck, "Design of wide-bandwidth Envelope-Tracking power amplifiers for OFDM applications", IEEE Tran. Microwave Theory and Techniques, vol. 53, no. 4, pp. 1244-1255, Apr. (2005).

[13] . D.Y.C. Lie, J. D. Popp, F. Wang, D. Kimball, and L.E. Larson, "Linearization of highly-efficient monolithic class E SiGe power amplifier with Envelope-Tracking (ET) and Envelope-Elimination-and-Restoration (EER) at 900MHz", Proc. IEEE Sixth Dallas Circuits and Systems Workship (DCAS), Dallas, USA, pp. 39-42, Nov. 15-16 (2007).

[14] . F. H. Raab, "Intermodulation distortion in Kahn- Technique transmitters", IEEE Trans. Microwave Theory and Techniques, vol. 44, no. 12, pp. 2273-2278, Dec. (1996).

[15] . J. Litva and T. K-Y. Lo, Digital Beamforming In Wireless Communication, Norwood, MA: Artech House, 1996.

[16] . A. J. Cann, "Nonlinearity model with variable knee sharpness", IEEE Tran. Aerosp. Electron. Syst., vol 16, no. 6, pp. 874-877, Nov. (1980).

[17] . J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman and T. Quach, "High efficiency CDMA RF power amplifier using dynamic envelope tracking technique", IEEE MTT-S Int. Microwave Symp. Dig., Boston, USA, pp. 873-976, June 11-16,2000.

[18] . S. L. Loyka, "On the Use of Cann's Model for Nonlinear Behavior-Level Simulation", IEEE Tran. Vehicular Technology, vol. 49, no. 5, pp. 1982-1985, Sept. (2000).

[19] . K. A. Remley, D.F. Williams, D.M.M.-R Schreurs and J. Wood, "Simplifying and interpreting two-tone measurements", IEEE. Trans. Microwave Theory and Techniques, vol. 52, no. 11, pp. 2576-2585, Nov. (2004).

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Research Paper

A Two-Stage Methodology of Network Reconfiguration for the Compensated Network

M. Damodar Reddy* , V.C. Veera Reddy**

*Associate Professor,Department of EEE.,S.V.University College of Engineering,Tirupati,A.P,India.

**Professor,Department of EEE.,S.V.University College of Engineering,Tirupati,A.P,India.

M.Damodar Reddy and V.C.Veera Reddy (2008). A Two-Stage Methodology of Network Reconfiguration for the Compensated Network. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 22-29. https://doi.org/10.26634/jee.1.4.373

Abstract

This paper delineates a two-stage methodology of network reconfiguration for the compensated network. A two-stage methodology is used to reduce the losses and to improve the voltage profile of the balanced radial distribution networks. In the first stage, capacitors are placed optimally for the reactive power compensation of the original network. Fuzzy approach is used to find the optimal capacitor locations and analytical method is used to find the sizes of capacitors. In the second stage, an improved fuzzy multi-objective algorithm is used for the network reconfiguration of the compensated network. The proposed method is tested on 33-bus and 69-bus test systems and the results are presented.

References

[1] . Baran M.E. and Wu F.F., "Optimal capacitor placement on radial distribution systems", IEEE Transactions on Power Delivery, vol.4, no-1, pp. 725-734, January 1989.

[2] . Baran M.E. and Wu F.F., "Optimal sizing of capacitors placed on a radial distribution system", IEEE Transactions on Power Delivery, vol.4, no-1, pp. 735-743, January 1989.

[3] . Hague M.H., "Capacitor placement in radial distribution systems for loss reduction", IEE Proceedings - Generation, Transmission and Distribution, vol. 146, pp. 501 -505, September 1999.

[4] . Ng H.N., Salama M.M.A. and Chikhani A.Y., "Classification of capacitor allocation techniques", IEEE Transactions on Power Delivery, vol. 15, no.l, pp. 387- 392, January 2000.

[5] . Ng. H.N., Salama M.M.A. And Chikhani A.Y., "Capacitor allocation by approximate reasoning: fuzzy capacitor placement" IEEE transactions on power delivery, vol. 15, No. 1, pp. 393 - 398, January 2000.

[6] . Civanlar S., Grainger J.J., Yin H., and Lee S.S.H., "Distribution feeder reconfiguration for loss reduction," IEEE Transactions on Power Delivery, vol. 3, no. 3, pp. 121 7-1223, Jul. 1988.

[7] . Baran M. E. and Wu F. F., "Network reconfiguration in distribution systems for loss reduction and load balancing," IEEE Transactions on Power Systems., vol. 4, no. 3, pp. 1401 -1407, Aug. 1989.

[8] . Ghosh S. and Das D., "An efficient algorithm for loss minimization via network reconfiguration". Electric Power Components & Systems, vol.31, no.8, pp. 791-804,2003.

[9] . Debapriya Das, "Afuzzy multi-objective approach for network reconfiguration of distribution systems" IEEE transactions on power delivery, vol. 21, No.l, pp. 202 - 209, January 2006.

[10] . Dan Jiang and Ross Baldick, "Optimal electric distribution system switch reconfiguration and capacitor control" IEEE Transactions on Power Systems, vol. 1 l,no. 2, pp. 890-897, May 1996.

[11] . Haque M.H., "Improvement of power delivery efficiency of distribution systems through loss reduction" Proceedings of IEEE PES Winter Meeting 2000, vol-4, pp. 2739-2744,2000.

[12] . Zhang Dong, Fu Zhengcai, Du Y. and Zhang Liuchun, "Capacitor switching and network reconfiguration for loss reduction in distribution system" Proceedings of IEEE PES General Meeting 2006, pp. 1-6, June 2006.

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Research Paper

Genetic Algorithm Based Optimum Reactive Power Dispatch for Voltage stability Enhancement in the Presence of FACTS devices

K. Vaisakh* , P.Kanta Rao**

* Professor, Department of Electrical Engineering, AU College of Engineering, Andhra University, Vlsakhapatnam, A.P, India.

** Professor, Department of Electrical and Electronics Engineering, SRKR College Of Engg, Bhlmavaram, W.G.DIst., A.P, India

K. Vaisakh and P.Kanta Rao (2008). Genetic Algorithm Based Optimum Reactive Power Dispatch for Voltage stability Enhancement in the Presence of FACTS devices. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 30-38. https://doi.org/10.26634/jee.1.4.376

Abstract

Reactive Power Dispatch (RPD) and voltage control of power systems is one of the important tasks in the operation and control of the power system. RPD problem can be formulated as a non-linear constrained optimization problem. This paper presents a Genetic Algorithm (GA) approach for solving the reactive power dispatch problem including the line flow constraint. Minimization of voltage Instability with FACTS and without FACTS devices is the objective of this reactive power optimization problem. The proposed algorithm has been applied to find the optimal reactive power control variables in IEEE 30 system in which the control of bus voltages, tap position of transformers and reactive power sources are involved to minimize the transmission loss in addition to improving the sum of square of load bus voltage stability indices. The simulation results are promising and show the effectiveness of the proposed RPD approach in the presence of FACTS device.

References

[1].Dommel, H.W., Tinney, W.F., (1968), Optimal power flow solutions. IEEE Trans, on Power Apparatus and Sysfems,87:1866-1876.

[2] . Hong, Y.Y., Sun, D.I., Lin, S.Y., Lin, C.J., (1990), Multi¬year multi-case optimal AVR planning. IEEE Trans. On Power Systems, 5(4): 1294-1301.

[3] . Yin, X., Germay, N., (1991), Investigations on solving the load flow problem by genetic algorithms. Electric Power System Research Journal, 22(3): 151 -163.

[4] . Iba, K., (1994), Reactive power optimization by genetic algorithm./FEE Trans, on Power System, 9(2):685- 692.

[5] . Wu, Q.H., Cao, Y.J., Wen, J.Y., (1998), Optimal reactive power dispatch using an adaptive genetic algorithm. Int. J. Elect.PowerEnergySyst., 20(8):563-569.

[6] . Wong, K.R, Wong, Y.W., (1994), Genetic and genetic/simulated-annealing approaches to economic dispatch./EEProc. Pt. C,141 (5):507-513.

[7] . Lee, K.Y., Bai, X.M., Park, Y.M., (1995), Optimization method for reactive power planning by using a modified genetic algorithm. IEEE Trans, on Power Systems, 10(4): 1843-1850.

[8] . Lee K.Y. Park Y.M. and Ortiz J.L. (1985), A United Approach to Optimal Real and Reactive Power Dispatch1, IEEE Trans, on Power Apparatus and Systems, May, Vol.PAS. 104, No.5, pp. 1147-1153.

[9] , Granville, S. (1994), 'Optimal reactive power dispatch through interior point methods1,. IEEE Trans, on Power Systems Vol. 9. No. 1 ,pp.98-l 05.

[10] . Iba K. (1994), 'Reactive power optimization by genetic algorithms', IEEE Trans on power systems. May, Vol.9, No.2, pp.685-692.

[11 ]. Wu Q.H. and Ma J. T. (1995), 'Power system optimal reactive power dispatch using evolutionary programming', IEEE Trans on power system, Aug, Vol. 10, No.3,pp.l 243-1249.

[12] . Bhagwan Das, Patvardhan C. (2003), 'A New Hybrid Evolutionary Strategy for Reactive Power Dispatch1, Electric Power Research, Vol.65. PR83-90.

[13] . Abido, M.A. and J. M. Bakhaswain (2003), A Novel Multi Objective Evolutionary Algorithm for Optimal Reactive Power Dispatch Problem. Proceedings of ICECS 2003 of IEEE.

[14] . Stephane Gerbex, Rachid Cherkaoui, andAlain J.Germond (2001), Optimal Location of Multi-type FACTS Devices in a Power System by Means of Genetic Algorithm1, IEEE Trans on Power System, Vol.16, No.3, pp.658-667,

[15] . Zhao B., Guo C.X. and Cao Y.J. (2005), A multiagent based particle swarm optimization approach for optimal reactive power dispatch1, IEEE Trans, on power system. May, Vol. 20.NO.2, pp.l 070-1078.

[16] . Singiresu S. Rao, 'Engineering Optimization-Theory and practice', III Edition, New age international pvt. ltd Publishers.

[17] . Kalymony Deb (2004) 'Optimization for engineering design algorithms and examples' Prentice Hall of India.

[18] . Mangoli, M.K., and Lee, K.Y., (1993) Optimal real and reactive power control using linear programming1, Electr. PowerSyst. Res., 26, pp. 110.

[19] . Scott, B., Alsac, O., Bright, J., and Paris, M., (1990) 'Further developments in LP-based optimal power flow1, IEEE Trans., 1990, PWRS-5, (3), pp. 697-711.

[20] . Lima.G.M.et al., (2003) 'Phase shifter placement in large-scale systems via mixed Integer programming', \EEE Trans., 2003, PWRS-18, (3), pp. 1029-1034.

[21] . Kumar, A., and Parida, S., (2005) 'Enhancement of power system Loadability with location of FACTS controllers in competitive electricity markets IEE Proc.- Gener. Transm. Distrib., Vol. 152, No. 6, November 2005.

[22] , R Kessel, H. Glavitsch, (1986) Estimating the voltage and lability of a power system, IEEE Trans. Power Deliv. vol. PWRD-1 (3) (July 1986) 346-354.

[23] . Lai, L. L., Ma, J. T., (1997), Application of evolutionary programming to reactive power planning-Comparison with nonlinear programming approach. IEEE Trans, on PowerSystems, 12(1): 198-204.

[24] . Das, D.B., Patvardhan, C., (2002), Reactive power dispatch with a hybrid stochastic search technique. Int. J. Elect. PowerEnergySyst., 24(9): 731 -736.

[25] . Clerc, M., Kennedy, J., (2002), The Particle SwarmExplosion, stability, and convergence in a multidimensional complex space. IEEE Trans, on Evol. Comput., 6(1):58-73.

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Research Paper

RF Phase Error Built-In-Self-Test for A GSM SOC

Dallas Webster* , Loi Phan, Oren Eliezer, Rick Hudgens, Donald Lie

Department of Electrical and Computer Engg,Texas University,Lubbock,Texas.

Texas Instruments,Inc,Dallas,Texas.

Senior Member of Technical Staff,Wireless Terminals Business Unit,Texas Instruments.

Section Manager,Wireless Terminals Business Unit,Texas Instruments.

*Associate Professor,Department of Electrical and Computer Engg,Texas University,Lubbock,Texas,USA.

Dallas Webster, Loi Phan , Oren Eliezer , Rick Hudgens and Donald Lie (2008). RF Phase Error Built-In-Self-Test for A GSM SOC. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 39-44. https://doi.org/10.26634/jee.1.4.378

Abstract

This paper presents a novel RF Built-in-Self-Test (RF-BiST) targeting to replace the traditionally expensive and time-consuming RF parametric phase error test on a GSM Digital Radio Processor (DRP) radio transceiver. The verification of the RF BiST in a production environment and a comparison of the internal BiST with two alternative external tests is presented, validating the RF BiST as an acceptable test method for determining the phase error of GSM devices. The results illustrate that there are great opportunities in reduction of test time and costs by moving to the internal digital method of the presented BiST for testing RF/analog IC products.

References

[1].R.B. Staszewski, J.L.Wallberg, S. Rezeq, H. Chih-Ming, O. Eliezer, et al. “All-digital PLL and transmitter for mobile phones", IEEE Journal of Solid-State Circuits, Vol. 40, Issue 12,pp. 2469-2482(2005).

[2]. O. Eliezer, I. Bashir, R.B. Staszewski, RT. Balsara, “Built-in Self Testing of a DRP-Based GSM Transmitter", IEEE Radio Frequency Integrated Circuits Symposium, pp. 339 -342, Honolulu, Hl, (2007).

[3]. M. Negreiros, L. Carro, A. Susin, “Digital Generation of Signals for Low Cost RF BIST", 12th IEEE European Test Symposium, pp. 49-54 Freiburg, Germany, (2007).

[4]. Y.C. Huang, H. Hsieh, L.H. Lu, "A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications", 25thIEEE VLSI Test Symposium, pp. 401 - 408, Berkeley, CA, (2007).

[5]. H. Hsieh, L.H. Lu, “Integrated CMOS power sensors for RF BIST applications", 24? IEEE VLSI Test Symposium, pp. 5, Berkeley, CA, (2006).

[6]. R.B. Staszewski, I. Bashir, andO. Eliezer, “RF Built-In Self Test of a Wireless Transmitter", IEEE Trans. Circuits and Systems II, 54, No. 2, pp. 186-190, (2007).

[7]. B. Lai, C. Rivera, K. Waheed, “Low Cost Testing of Quadruple Band GSM RFCMOS SoC", International Symposium on VLSI Design, Automation and Test, pp. 1 -4, Hsinchu, Taiwan, (2007).

[8]. 8960 GSM/GPRS/EGPRS Online User's Guide, Agilent 2007,http://wireless.agilent.com/rfcomms/refdocs/gsm/gprs/meas_pfer_desc.php.

[9].R.B.Staszewski,K.Muhammed and O.Eliezer,"Digital RF Processor (DRP)for Mobile Phones",IEEE Radio Frequency integrated Circuits Symposium,pp181-184,Honolulu,HI (2007)

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Research Paper

Optimal Design of Poly-Phase Induction Motor Using Particle Swarm Optimization

C.Thanga Raj* , S.P. Srivastava, Pramod Agarwal*

* Research Scholar, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.

Associate Professor, Department of Electrical Engineering, Indian Institute ofTechnology Roorkee, India.

* Professor, Department of Electrical Engineering, Indian Institute ofTechnology, Roorkee, India.

C.Thanga Raj, S.P. Srivastava and Pramod Agarwal (2008). Optimal Design of Poly-Phase Induction Motor Using Particle Swarm Optimization. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 45-50. https://doi.org/10.26634/jee.1.4.380

Abstract

This paper presents an optimal design of poly-phase induction motor using Improved Particle Swarm Optimization i.e. Quadratic Interpolation based Particle Swarm Optimization (QI-PSO) proposed in [21]. The optimization algorithm considers the cost of active materials, efficiency, starting torque, and temperature rise as objective function (which are considered separately) and nine performance related items as constraints. The QI-PSO algorithm was implemented on two test motors and their results are compared with the Simulated Annealing (SA) technique, Constrained Rosen Brock Method, Standard Particle Swarm Optimization (SPSO), and normal design. From the test results QIPSO gave better results and more suitable to motor’s design optimization. The effects of unbalanced stator voltage in the motor torque, temperature rise and efficiency are also tabulated.

References

[1] . D. G. Bharadwaj, K. Venkatesan, R. B. Saxena, Induction motor Design Optimization using Constrained Rosenbrock Method (Hill Algoritm), Computer and Electrical Engineering, 6,1979,41 -46.

[2] . Z. Maljkovic, M. Cettolo et.al, The Impact of the Induction Motor on Short-Circuit Current, IEEE Ind. Application Magazine, 2001,11-17.

[3] . M. K. Yoon, C. S. Jeon, S. K. Kauh, Efficiency Increase of an Induction Motor by Improving Cooling Performance, IEEE Trans. Energy Conversion, 17, 2002,1- 6.

[4] . R. H. A. Hamid, A. M. A. Amin, R. S. Ahmed, A. El- Gammal, New Technique for Maximum Efficiency of Induction Motors Based on PSO, IEEE conference proceedings, 2006,2176-2181.

[5] . B. Pryymak et al., Neural Network based Flux Optimization using a Model of Losses in Induction Motor Drives, Mathematics and computers in simulation, 71, 2006,290-298.

[6] . S. Urn, K. Nam, "Loss Minimization Control Scheme for Induction Motors, IEE proc. Electric Power applications, 151(4), 2004,385-397.

[7] . S. Ghozzi, K. Jelassi, X. Roboam, Energy Optimization of Induction Motor Drives, IEEE conference on Industrial Technology(ICIT), 2004, pp. 602-610.

[8] . K. Sundareswaran et al., Artificial Neural Network based Voltage Controller for Energy Efficient Induction Motor Drives, IEEE Inf. Conference, 1998.

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Research Paper

Duty Ratio Based Space Vector Modulation for Current Source Inverter fed Induction Motor Drive

P.Parthiban* , Pramod Agarwal, S.P. Srivastava*

* Research Scholar, Indian Institute of Technology, Roorkee, India.

Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.

* Associate Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.

P.Parthiban, Pramod Agarwal and S.P. Srivastava (2008). Duty Ratio Based Space Vector Modulation for Current Source Inverter fed Induction Motor Drive. i-manager’s Journal on Electrical Engineering, 1(4), Apr-Jun 2008, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 51-56. https://doi.org/10.26634/jee.1.4.381

Abstract

In this paper duty ratio based space vector modulation for current source inverter fed induction motor drive is discussed. The control system of the induction motor is realized using direct vector control including field weakening region. Space vector modulation is the preferred PWM method for three phase current source inverters. A simplified SVM implementation that is based on calculation of duty ratio required to synthesize the reference current. The steady state and dynamic results of the proposed strategy are presented. The proposed scheme has the advantage of space vector modulation with fast dynamic response.

References

[1] . J. R. Espinoza, G. Joos, "Current-source inverter fed induction motor drive system with reduced losses," IEEE Industry Applications 30th IAS Annual Meeting, Vol.l, pp. 45-52, October 1995.

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[3] . Bimal K. Bose, Modern Power Electronics and AC Drives. (4th Indian Reprint): Pearson Education, 2002, pp. 356-384.

[4] . R. Krishnan, Electric Motor Drives. (2nd Indian Reprint): Prentice- Hall of India, 2003, pp.411-512.

[5] . H. Le-Huy, "Case Study: Variable frequency induction motor Drive", [Online], Available: http://www.mathworks.com/access/helpdesk_ 13 /help/toolbox/physmod/powersys/studcl 3.html.

[6] . Chern-Lin Chen, Che-Ming Lee, Rong-jie Tu and Guo-kiang Horng, "A novel simplified space-vector modulated control scheme for three-phase switch¬mode rectifier," in Proc. 1998 Power Electronics Specialists Conf., pp. 1358-1361.

[7] . A. Bakhshai, J. Espinoza, G. Joos, H. Jin, "Acombined artificial neural network and DSP approach to the implementation of space vector modulation techniques", in Proc. 1996 Industry Applications Conference., pp. 934-940.

[8] . M. Salo, H.Tuusa, "Experimental results of the current- source PWM inverter fed induction motor drive with an open-loop stator current control," in Proc. 2003 Applied Power Electronics Conference and Exposition, pp. 839-845.

[9] . Dong-Choon Lee, Dong-Hee Kim, Dae-Woong Chung, "Control of PWM current source converter and inverter system for high performance induction motor drives," in Proc. 1996 Industrial Electronics, Control, and Instrumentation conference., pp. 1100-1105.

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Volume 1 Issue 4 April - June 2008

Tom Page*

* Lecturer, Department of Design and Technology, Loughborough University Loughborough, Lelcs, UK.

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K. Vaisakh* , P.Kanta Rao**

* Professor, Department of Electrical Engineering, AU College of Engineering, Andhra University, Vlsakhapatnam, A.P, India. ** Professor, Department of Electrical and Electronics Engineering, SRKR College Of Engg, Bhlmavaram, W.G.DIst., A.P, India

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Dallas Webster* , Loi Phan**, Oren Eliezer***, Rick Hudgens****, Donald Lie*****

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C.Thanga Raj* , S.P. Srivastava**, Pramod Agarwal***

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P.Parthiban* , Pramod Agarwal**, S.P. Srivastava***

* Research Scholar, Indian Institute of Technology, Roorkee, India. ** Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India. *** Associate Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.

Abstract

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Jacob Day* , Paul Vulpoiu, Jeffery Julich*, Donald Lie****

Department of Electrical and Computer Engg.,Texas Tech,University,Lubbock,TX,U.S.A

,,Texas Instruments Inc.Dallas,TX,U.S.A.

****Associate Professor,Department of Electrical and Computer Engg.,Texas Tech,University,Lubbock,TX,U.S.A

Yan Li* , Jerry Lopez, Donald Lie*

*Associate Professor,Department of EEE.,S.V.University College of Engineering,Tirupati,A.P,India.

**Professor,Department of EEE.,S.V.University College of Engineering,Tirupati,A.P,India.

* Professor, Department of Electrical Engineering, AU College of Engineering, Andhra University, Vlsakhapatnam, A.P, India.

** Professor, Department of Electrical and Electronics Engineering, SRKR College Of Engg, Bhlmavaram, W.G.DIst., A.P, India

Dallas Webster* , Loi Phan, Oren Eliezer, Rick Hudgens, Donald Lie

C.Thanga Raj* , S.P. Srivastava, Pramod Agarwal*

P.Parthiban* , Pramod Agarwal, S.P. Srivastava*

* Research Scholar, Indian Institute of Technology, Roorkee, India.

Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.

* Associate Professor, Department of Electrical Engineering, Indian Institute of Technology, Roorkee, India.