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i-manager's Journal on Electrical Engineering (JEE)

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PV-grid Performance improvement through Integrated Intelligent Water Drop Optimization with Neural Network for Maximum Power Point Tracking
A Digital Healthcare Monitoring System with Real-Time Analysis
Advancements in Smart Meter Design and Integration for Enhanced Energy Management and Efficiency
Electric Vehicles in Modern Transportation: Environmental Impacts, Configurations, and Future Trends – A Review
GTO Technique Based Hybrid Power System Controller Design

Most Cited

Volume 4 Issue 3 January - March 2011

Article

A Survey on Hardware and Software Optimization of Microprocessors for Low Power Consumption

Ananthi Kaliyamoorthy* , S. Manoharan**

* Assistant Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore.

**Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore.

Ananthi Kaliyamoorthy, and S. Manoharan (2011). A Survey On Hardware And Software Optimization Of Microprocessors For Low Power Consumption. i-manager’s Journal on Electrical Engineering, 4(3), 1-9. https://doi.org/10.26634/jee.4.3.1393

Abstract

Today there is a growing need for reducing the power consumption of microprocessors, because they form a major share of the power budget of equipment. Power consumption in microprocessors can be reduced either by hardware, software or both. The power consumption of the processors increases along with increase in transistor count and clock frequencies. Thus there is a need to design a processor which consumes less power without affecting its performance and efficiency. Likewise, each instruction involves specific part of the microprocessor. Therefore, by selecting the correct instruction it is possible to reduce the power consumed by the processor. This paper presents a survey on hardware and software power reduction techniques used for several microprocessors.

References

[1]. Venkatachalam, V. and Franz, M. (2005). “Power Reduction Techniques For Microprocessor Systems”, ACM Computing Surveys, Vol. 37, No. 3, September, pp. 195–237.

[2]. Stephen H Gunther, Frank Binns, Douglas M. Carmean, Jonathan C. Hall, “Managing the Impact of Increasing Microprocessor Power Consumption”, Desktop Platforms Group, Intel Corp.

[3]. Washer, S. “Dynamic Power Reduction in a Microprocessor”.

[4] Hattori, T. (2003). “Design Methodology of Low-Power Microprocessors”, Design Automation Conference, Proceedings of the ASR – DAC, Asia and South Pacific. Hitachi, Ltd. PP, 390-393

[5]. Bill Moyer, “Low-Power Design for Embedded Processors”, Proc. IEEE, Vol. 89 Issue: 11 pp. 1576 -1587, Nov. 2001

[6] Dan Dobberpuhl, (1996). “The Design of a High Per formance Low Power Microprocessor ”. Proc. International Symposium on Low Power Electronics and Design.

[7]. Oh, J., & Pedram, M. (2001). “Gated Clock Routing for Low-Power Microprocessor Design”, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, June, Vol. 20, No. 6, pp.715-722.

[8]. Oh J., & Pedram M., (1998). “Power reduction in microprocessor chips by gated clock routing,” in Proc. Asia South Pacific Design Automation Conf., Jan. 1998, pp. 313–318.

[9]. Sulaiman, D R. (2008). “Using Clock gating Technique for Energy Reduction in Portable Computers”, IEEE C, Computer and Communication Engineering, pp 839- 842.

[10]. Hai Li, Bhunia, S., Yiran Chen, Kaushik Roy, Fellow, IEEE, & Vijaykumar T. N., (2004). “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, March, Vol. 12, No. 3, pp 245-254.

[11]. Shan Li, Edmund M K Lai, Absar, M J. (2003). “Minimizing Embedded Software Power Consumption through Reduction of Data Memory Access”, IEEE conf. pp 309-313.

[12]. Ravindran R A., Nagarkar P D., Dasika G S., Marsman E D., Senger R M., Mahlke S A., & Brown R B., (2005) “Compiler managed dynamic instruction placement in a low-power code cache,” International Symposium on Code Generation and Optimization, pp 179 – 190.

[13]. Zambreno J., Kandemir M T., & Choudhary A., (2002). “Enhancing compiler techniques for memory energy optimizations,” Embedded Software. Second International Conference, EMSOFT 2002, 2491:364 – 381.

[14]. Mehta H., Owens R., Irwin M., Chen R., & Ghosh D., (1997). “Techniques for low energy software,” ISLPED - International Symposium on Low Power Electronics and Design, pp 72 – 75.

[15]. Leupers R., (2001). “Code generation for embedded processors,” The 13thInternational Symposium on System Synthesis, Sept, pp 173 – 178.

[16]. Mohan G. Kabadi, Kannan, N., Chidambaram, P., Suriya Narayanan, Subramanian M., & Ranjani, P., “Dead-Block Elimination in Cache: A Mechanism to Reduce I-cache Power Consumption in High Performance Microprocessors”, School of Computer Science and Engineering, Anna University.

[17]. Tiwari V., Malik S., Wolfe A., (1994). “Power analysis of embedded software: a first step towards software power minimization,” Proceedings of the IEEE Conf. on Computer Aided Design, Santa Clara CA Nov, pp. 384- 390.

[18]. Russell J T., & Jacome M F., (1998). “Software power estimation and optimization for high performance, 32-bit embedded processors,” International Conference on Computer Design: VLSI in Computers and Processors, pp 328 – 333.

[19]. David A. Ortiz, Nayda G. Santiago, (2010). “High- Level Optimization for Low Power Consumption on Microprocessor-Based Systems”.

[20]. Oscar Acevedo, Dr. Manuel Jimenez, (2010). “A Survey of Software Optimization Techniques for Low-Power Consumption”.

[21]. Sarta, D., Trifone, D., Ascia, G. (1999). “A data dependent approach to instruction level power estimation”. Low-Power Design,1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on, pp (s): 182 -190

[22]. Wiratunga, S., Gebotys C. (2000). “Methodology for minimizing power with DSP code”. Electrical and Computer Engineering, 2000 Canadian Conference on, pp. 293 -296 vol.1.

[23]. Brennan, P., Dean, A., Kenyon, S. and Ventrone, S. (1998). “Low Power Methodology and Design Techniques for Processor Design”, ACM conf. pp. 268-273

[24]. Tiwari, V., Malik, S., Wolfe, A. (1994), “Compilation techniques for low energy: an overview”. Low Power Electronics,1994. Digest of Technical Papers., IEEE Symposium, pp: 38 –39.

[25]. Vivek De and Borkar, S. ”Technology and Design Challenges for Low Power and High Performance”, Intel Corporation. pp 163-168.

[26]. Suresh, R. (I996). “Challenges in Low-Power Microprocessor Design”, Microprocessor Technology, Intel Corporation, 9th International Conf. on VLSI Design, Jan pp 329-330.

[27]. Lichtenau, C., (2005). Alberto Garcia Oruz, Pfliiger, T. “Technological and Architectural Power Optimizations for Advance Microprocessors” IEEE conf. pp.11-14.

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Research Paper

A Low Cost Microcontroller Based Triggering Circuit for Multilevel Inverter

Adil Sarwar* , M.S. Jamil Asghar**

* Research Scholar, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India.

** Professor, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India.

Adil Sarwar, and M.S. Jamil Asghar (2011). A Low Cost Microcontroller Based Triggering Circuit For Multilevel Inverter. i-manager’s Journal on Electrical Engineering, 4(3), 10-16. https://doi.org/10.26634/jee.4.3.1394

Abstract

Multilevel inverters have drawn increasing attention in recent years, especially in the distributed energy resources area. Several renewable energy sources (batteries, fuel cells, solar cells, wind turbines or micro turbines) can be easily connected through a multilevel inverter to feed a load (off-grid) or interconnect to the ac grid (grid-tie) without voltage balancing problems. Moreover, multilevel inverters have a lower switching frequency than standard PWM inverters and thus have reduced switching losses. The output waveforms of multilevel inverters are in a stepped form, resulting in reduced harmonics compared to a square-wave inverter. In the present work, PIC 16F877A microcontroller based triggering circuit has been designed to be used with various levels of multilevel inverter. Multiple pulses with relative delay and requirement of a single variable dc supply (0-5V) for the control of all delay angles, makes it cost effective and simple. In addition, PIC 16F877A are cheaper with respect to other 8 bits microcontrollers available in market. It is a RISC controller with only 25 instruction sets. The Harvard architecture makes it more attractive. The simulation is done using MPLAB IDE and PROTEUS 7. Practical circuit has been designed and successfully implemented.

References

[1]. J. Kumar, B. Das and A. Pramod, (2008). “Selective Harmonic Elimination Technique for a Multilevel Inverter”, Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December, pp. 608-613.

[2]. J. Iwaszkiewicz and B. J. Perz, (2005). “Multilevel Convertors for Distributed Power Generation Systems with DC Voltage Sources”, International Conference on Renewable Energies and Power Quality (ICREPQ), Saragossa, pp. 292-297.

[3]. L. M., Tolbert, F. Z., Peng, T. G., Habetler. (1999). “Multilevel converters for large electric drives,” IEEE Transactions on Industry Applications, Vol.35, No. 1, Jan/Feb, pp. 36-44.

[4]. J. S. Lai and F. Z. Peng, (1996). “Multilevel converters – A new breed of power converters,” IEEE Transactions on Industry Applications, Vol. 32, No.3, May/June, pp. 509- 517.

[5]. M. Tolbert, J. N. Chiasson, Z. Du, K. J. L. McKenzie, (2005). “Elimination of Harmonics in a Multilevel Converter With Non equal DC Sources”, IEEE trans. on industry applications, Vol. 41, No. 1, January/February, pp. 75-82.

[6]. A. Myrzlk, M. A. Johanna, (2001). “Novel inverter topologies for single-phase stand-alone or grid connected photo-voltaic systems”. International Conference on Power Electronics and Drives System (IEEE PEDS), Bali, October, pp. 103-108.

[7]. M.S.J. Asghar, (2004). “Power Electronics”, PHI learning, India, chapter 6.

[8]. A. Sarwar, M.S.J.Asghar, Imdadullah and S.K.Moin Ahmed, (2009). “Development of solar PV based grid connected inverters”, International Conference on Electrical Energy System & power Electronics (ICEESPEEE09), Kattankulathur, April, pp.1172-1177.

[9]. Petchjatuporn, P.; Ngamkham, W.; Khaehintung, N.; Sirisuk, P., Kiranon, W., Kunakorn, A., (2005). "A Solarpowered Battery Charger with Neural Network Maximum Power Point Tracking Implemented on a Low-Cost PICmicrocontroller," TENCON IEEE Region 10, Vol, No. pp.1-4, 21-24 Nov.

[10]. Anani, N., O'Reilly, D., Williamson, J., Ponnapalli, P., (2010). "Minimisation of line current harmonics in singlephase. AC-DC converter using a microcontroller, " Universities Power Engineering Conference (UPEC), International, pp.1-5, Aug.

[11]. “Datasheet PIC16F877A” available at ww1.microchip.com/downloads/en/devicedoc/39582b. pdf.

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Research Paper

A 10-bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method

Weibo Hu * , Donald Lie**

* Research Scholar, ECE Department of Texas Tech. University, Lubbock.

** Associate Professor, ECE Department of Texas Tech. University, Lubbock.

Weibo Hu and Donald Y.C. Lie (2011). A 10-Bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method. i-manager’s Journal on Electrical Engineering, 4(3), 17-22. https://doi.org/10.26634/jee.4.3.1395

Abstract

A 10-bit single-ended ultra-low-power Successive Approximation Register ADC with a novel DAC switching technique is designed in the TSMC 0.18µm mixed-signal CMOS technology. This method uses a reference voltage of VR/2, rather than VR, as the only reference voltage to digitize the input signals with the amplitude range of [0, VR]. Compared with the conventional switching method, this work reduces the size of binary-weighted capacitor array by 50%, lowering the average power consumption in the DAC during digitizing by 87.5%, and it also reduces the power consumption during sampling by 63.5%. With the sampling frequency of 77 kHz, ADC’s post-layout simulation resolution is 8.84 bits and ERBW (Effective Resolution Bandwidth) is 60 kHz, and the post-layout simulation FOM of our 10-bit SAR ADC can reach 18.9 fJ/(conversion-step), which is among the best ADCs FOM reported in a CMOS 0.18 µm technology.

References

[1]. R. E. Suarez, P. R. Gray., and D. A. Hodges, (1975). “All- Mos Charge Redistribution Analog-to-Digital Conversion Techniques-Part 1,” IEEE J. Solid-State Circuits, Dec. Vol. 10, No. 6, pp. 379-385.

[2]. M. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink1., and B. Nauta, (2008). “A 1.9?W 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” ISSCC Dig. Tech. Papers, pp. 243-245, San Francisco, USA. Feb.

[3]. E. Culurciello., and A. G. Andreou, (2006). “An 8-bit 800?W 1.23-MS/s Successive Approximation ADC in SOI CMOS,” IEEE Tran. Circuit and Systems-II, Sep. Vol. 53, No. 9, pp. 858-891.

[4]. B. P. Ginsburg., and A. P. Chandrakasan, (2005). “An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitor DAC,” May, Proc. IEEE ISCAS, pp. 184–187, Kobe, Japan.

[5]. C.C. Liu, S.J. Chang, G.Y. Huang., and Y.Z. Lin, (2010). “A 10-bit 50Ms/s SAR ADC with a Monotonic Capacitor Switching Procedure,” Apr. IEEE J. Solid-State Circuits, Vol. 45, No. 4, pp. 731-740.

[6]. V. Hariprasath, J. Guerber, S.-H. Lee., and U. -K. Moon, (2010). “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,”Apr. Electronics Letters, Vol. 46, No. 9, pp. 620-621.

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Research Paper

A 3P-3W UPQC integrated with Star-Hexagon Transformer for 3P-4W Distribution System

Yash Pal* , A. Swarup, Bhim Singh*

* Assistant Professor,Department of Electrical Engineering, National Institute of Technology, Kuruksetra, Haryana

Professor, Department of Electrical Engineering, National Institute of Technology, Kuruksetra, Haryana.

* Professor, Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India.

Yash Pal, A. Swarup and Bhim Singh (2011). A 3p-3w Upqc Integrated With Star-Hexagon Transformer For 3p-4w Distribution System. i-manager’s Journal on Electrical Engineering, 4(3), 23-31. https://doi.org/10.26634/jee.4.3.1396

Abstract

In this paper, a new topology is proposed for a three-phase four-wire (3P4W) distribution system utilizing a star-hexagon transformer along with three-phase three-wire (3P3W) Unified Power Quality Conditioner (UPQC).In this proposed topology the neutral point of the star connected transformer, used for the connection of series active power filter (APF) of 3P3W UPQC, is utilized as a fourth wire for 3P4W distribution system. The star-hexagon transformer is connected near the load to compensate the neutral current that may flow toward the neutral point of the series transformer of series APF. The series and shunt APF of 3P-3W UPQC are realized by readily available three-leg voltage source inverters (VSIs). For the mitigation of different power quality problems a control technique based on synchronous reference frame (SRF) theory is used for the control of UPQC. In this control scheme of UPQC, the current/voltage control is applied over the fundamental supply currents/voltages instead of fast changing APFs currents/voltages, there by reducing the computational delay. With the connection of star-hexagon transformer, no extra control is required for the neutral current; hence required numbers of current sensors are reduced. The performance of the proposed topology of UPQC is analyzed through simulations results using MATLAB software with its Simulink and Power System Block set toolboxes.

References

[1]. E.W Gunther., and Mehta H., (1995). “A survey of distribution system power quality,” IEEE Trans. Power Delivery, Vol.10, No.1, pp.322-329, Jan.

[2]. A.C.Liew, (1989). “Excessive neutral current in threephase fluorescent lighting circuits,”IEEE Trans.Ind. Appl., Vol.25, No.4, pp.776-782.Jul. /Aug.

[3]. T.M.Gruzs, (1990). “A survey of neutral currents in three-phase computer systems, “IEEE Trans. Ind. Appl.,Vol.26, No.4,pp.719-725,Jul./Aug.

[4]. IEEE recommended practices and requirements for harmonic control in electric power system, Dec. IEEE Std.519, 1992.

[5]. IEEE Recommended Practice for Electric Power Distribution for Industrial plants, IEEE Std.141, 1993.

[6]. Arindam Ghosh, Gerard Ledwich, (2002). “Power Quality Enhancement Using Custom Power Devices” Kluwer International Series in Engineering and Computer Science.

[7]. Jayaprakash P., Singh B., and Kothari D.P., (2008). “Star/Hexagon transformer Based Three-Phase Four-Wire DSTATCOM for Power Quality Improvement,” International Journal of Emerging Electric Power System, Vol.9, No.8, Article1, Dec.

[8]. J. Praveen, B.P. Muni, S. Venkateshwarlu., and H.V. Makthal, (2004). “Review of Dynamic Voltage Restorer for Power Quality Improvement,” Proc. IEEE IECON2004, Nov. Vol.1, pp.749-754.

[9]. B. Han, B. Bae, H. Kim and S. Baek, (2006). “Combined Operation of Unified Power-quality Conditioner with Distributed Generation,” IEEE Trans. Power Del., Vol. 21, No. 1, pp. 330–338, Jan.

[10]. T. Zhili, L.Xun, C. Jian, K.Y ong., and D. Shanxu, (2006). “A direct control strategy for UPQC in three-phase four-wire system,” in Proc. IEEE Conf. on Power Electron. and Motion Control Vol.2,pp.1-5.

[11]. V. Khadkikar., and A.Chandra., (2009). “A Novel Structure for Three-Phase Four-Wire Distribution System Utilizing Unified Power Quality Conditioner (UPQC),”IEEE Trans. Industry Appl., Vol.45, pp.1897-1902.

[12]. L. Xun., Z. Guorong., D. Shanxu., and C.J.Chen, (2007). “Control Scheme for Three-Phase Four-Wire UPQC in a Three-Phase Stationary Frame,” Procd.IEEE/IECON 2007, pp.1732-1736.

[13]. A.Ghosh, A.K.Jindal., and A.Joshi, (2004). “A unified power quality conditioner for voltage regulation of critical load bus,” in Proc. IEEE Power Eng. Society General Meeting, June, Vol.1, pp471-476.

[14]. B.Singh., and Venkateswarlu, (2010). “A Simplified Control Algorithm for Three-Phase Four-Wire Unified Power Quality Conditioner,” Journal of Power Electronics, Jan. Vol.10, No.1.

[15]. G.Chen, Y.Chen., and K.M.Smedley, (2004). “Threephase four-leg active power quality conditioner without references calculation,” in Procd. IEEE APEC, Vol.1, pp.587-593.

[16]. V. Kumar, P. Agarwal and H. O. Gupta., “A Simple Control Strategy for Unified Power Quality Conditioner Using Current Source Inverter,” in Procd. IPEC2007, pp.1219-1223.

[17]. B. Singh, S. Gairola, B. N. Singh, A. Chandar and K. Al-Haddad, (2008). “Multipulse AC-DC Converters for improving Power Quality: A Review,” IEEE Trans. On Power Electronics, Jan. Vol.23, No.1, pp.260-281.

[18]. B. Singh, S. Gairola, B. N. Singh, A. Chandar and K.Al-Haddad, (2007).“Power Quality Improvements in Isolated Twelve-Pulse AC-DC Converters using Delta/Double-Polygon transformer,” in Procd. of IEEE PESC, June ,pp.2848-2853.

[19]. B. N. Singh, P. Rastgoufard, B. Singh , A. Chandra and K.A. Haddad., (2004). “Design, simulation and implementation of the three pole/four pole topologies for active filters,” in Inst. Elect. Engg. Proc. Electr. Power Appl., Jul. Vol.151, No.4, pp.467-476.

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Research Paper

Distribution Network Planning with Advanced Centralized Voltage Regulation System

Sankar S*

Senior Lecturer, Panimalar Institute of Technology, Chennai.

S. Sankar (2011). Distribution Network Planning With Advanced Centralized Voltage Regulation System. i-manager’s Journal on Electrical Engineering, 4(3), 32-37. https://doi.org/10.26634/jee.4.3.1397

Abstract

Traditional voltage regulation systems for distribution networks fail to achieve their objective in presence of local generation resources as they are designed for passive distribution systems and based on assumptions that may not hold if distributed generation (DG) is connected to the network. An advanced centralised voltage regulation system has been studied by the Authors to allow a greater DG penetration and a high quality service to customers. However, depending on the characteristics of the specific network, it could be sometimes impossible to solve some operating conflicts between voltage regulation and correct DG operation. In practice, in order to connect a greater amount of DG, it might be necessary, not only to revise the employed regulation criteria, but also to act at the planning stage to make specific changes in the structure of a distribution system. In this view the paper presents a planning procedure that, besides existing distribution system data bases, load variation forecast, environmental/climatic conditions, and planners experience, takes into account information directly provided by the operation of the aforementioned advanced voltage regulation system.

References

[1]. Directive 2001/77/EC of the European Parliament and of the Council of 27 September 2005 on the promotion of electricity produced from renewable energy sources in the internal electricity market.

[2]. Directive 2006/54/EC of the European Parliament and of the Council of 26 June 2006 concerning “Common Rules for the Internal Market in Electricity” and Repealing Directive 96/92/EC.

[3]. European Technology Platform “Smart Grids”,

[4]. S. Conti, A.M. Greco, (2007). “Innovative Voltage Regulation Method for Distribution Networks with Distributed Generation”, in Proc. of the 19th International Conference on Electricity Distribution (CIRED), 21-24 May, Vienna, Austria.

[5]. S. Conti, S. Raiti, G. Tina, (2005). “Small-Scale Embedded Generation Effect on Voltage Profile: an Analytical Method”, IEE Proc. on Generation, Transmission and Distribution, Vol. 150, No. 1, pp. 78-86, January.

[6]. S. Conti, S. Raiti, G. Tina, U. Vagliasindi, (2006). “Integration of multiple PV units in urban power distribution systems”, Solar Energy, Vol. 75, pp. 87-94.

[7]. S. Conti, A. Greco, N. Messina, S. Raiti, (2006). “Local Voltage Regulation in LV Distribution Networks with PV Distributed Generation”, in Proc. of SPEEDAM Symposium 23-26 May, Taormina, Italy (on CD-ROM - S17, pp. 23-28).

[8]. S. Conti, G. Tina, (2007). “Reliability Worth Assessment for Distribution Systems: Automated Versus Traditional Configurations”, International Journal of Power and Energy Systems, Vol. 26, No.2, pp. 124-136.

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Research Paper

Mobile Voting System using Iris Recognition and Cryptography Techniques

K. Gopal* , S. Praveen, N. Suthanthira Vanitha*

, BE. II-EEE, Knowledge Institute of Technology, Salem, India.

Professor, Department of EEE, Knowledge Institute of Technology, Salem, India.

K. Gopal, S. Praveen and N. Suthanthira Vanitha (2011). Mobile Voting System Using IRIS Recognition And Cryptography Techniques. i-manager’s Journal on Electrical Engineering, 4(3), 38-42. https://doi.org/10.26634/jee.4.3.1398

Abstract

With the advancement of electronics and computer science, mobile communication technology leads us to a fast moving entirely different world. In this scenario, we have lot of responsibilities, one of it is voting for our country, but even we don’t have time for it, and also our votes may not useful to our nation, because of fake votes and cheating process happened during the election. This problem is rectified by the latest voting system as “Mobile Voting System” which is discussed in this paper. The mobile voting system uses the efficient techniques, iris recognition and cryptography for the secured voting process. The iris recognition and cryptography avoids the fake votes and cheating process. The election commission spends lot of money, for each election unnecessarily, which will be minimized by this system. This system enables the voter to vote to the Nation from his place itself.

References

[1]. John D. Woodward (Jr.), Nicholas M.Orlans, PeterT.Higgins (2003). “Biometrics” The Mc-Graw Hill Companies.

[2]. Anil K. Jain, Patrick Joseph Flynn, Arun Abraham Ross (2008). “Handbook of biometrics” Springer.

[4]. William Stallings. (2010). “Cryptography and Network Security, Principles and Practice”, Pearson Publications.

[5].I.A.Dhotre V.S.Bagad “Information Security”, http://books.google.co.in/books.

[6].Paul Reid “Biometrics for network security”, http://books.google.co.in/books.

[7].Behrouz A. Forouzan,”Cryptography and network security” 2008 http://books.google.co.in/books.

[8]. S. Kami Makki, Peter Reiher, Kia Makki (2007). “ Mobile and wireless network security and privacy”- 2007.

[9]. Friedhelm Hillebrand, Finn Trosby, Kevin Holley, Ian Harris ( 2010). “Short Message Service (SMS): The Creation of Personal Global Text Messaging”

[10].Krzysztof Wesolowski (2002).“Mobile communication systems”. http://books.google.co.in/ books.

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Research Paper

Adaptive Neuro-Fuzzy Dividing Frequency Controlfor the Development of Hybrid Active Power Filter

M. S. Sujatha* , T. Susritha, Vijay Kumar*

, Research Scholar, Department of EEE,SVEC, A.Rangampeta, Tirupati.

Professor, Department of EEE, JNTUCEA, Ananthpur.

M.S. Sujatha, T. Susritha and M. Vijay Kumar (2011). Adaptive Neuro-Fuzzy Dividing Frequency Control For The Development Of Hybrid Active Power Filter. i-manager’s Journal on Electrical Engineering, 4(3), 43-53. https://doi.org/10.26634/jee.4.3.1399

Abstract

This paper deals with a hybrid active power filter with injection circuit (IHAPF). It shows great promise in reducing harmonics and improving the power factor with a relatively low capacity active power filter. To minimize the capacity of IHAPF, an adaptive fuzzy dividing frequency-control method is proposed which consists of two control units: a generalized integrator control unit and fuzzy adjustor unit. The generalized integrator is used for dividing frequency integral control, while fuzzy arithmetic is used for adjusting proportional-integral coefficients timely. And the control method is generally useful and applicable to any other active filters. Compared to other IHAPF control methods, the adaptive fuzzy dividing frequency control shows the advantages of shorter response time and higher control precision. The simulation and experimental results shows that the new control method is not only easy to be calculated and implemented, but also very effective in reducing harmonics. In this paper Adaptive Neuro-Fuzzy controller is also used to develop the Hybrid Active Power Filter which has the advantages of reduced rule-base and fast response compared to Adaptive Fuzzy dividing frequency control method [1].

References

[1]. A.Luo, Z.Shuai, W.Zhu, C.Tu. (2009). “Development of Hybrid Active Power Filter Based on the Adaptive Fuzzy Dividing Frequency-Control Method”, IEEE Trans. Power Del,Jan, Vol 24, No.1, 424-432, January.

[2]. L. Gyugyi and E. C. Strycula, (1976). “Active Ac power filters,” in Proc. IEEE, Ind. Appl. Soc. Annu. Meeting, pp. 529–535.

[3]. N. Mohan, H.A. Peterson, W.F. Long, G.R. Dreifuerst,and J.J. Vithayathil, (1977). “Active filters for AC harmonic suppression,” presented at the IEEE Power Eng. Soc. Winter meeting, pp 168-174.

[4]. F. Peng, H. Akagi, and A. Nabae, (1990). “A new approach to harmonic compensation in power system-a combined system of shunt passive and series active filters,” IEEE Trans. Ind. Appl. Nov, Vol26, No.6, pp. 983- 990,Nov.

[5]. C. Madtharad and S. Premrudeepreechacharn, (2002). “Active power filter for three-phase four-wire electric systems using neural networks,” Elect. Power Syst. Res. Apr., Vol.60, No. 2, pp.179-192.

[6]. H. Fujita and H. Akagi, (1991). “a practical approach to harmonic compensation in power system-series connection of passive and active filters,” IEEE trans Ind. Appl. Nov., Vol27, No.6, pp.1020-1025.

[7]. S. Kim and P.N. Enjeti, (2002). “A new hybrid active power filter (APF) topology,” IEEE trans. Power Electronics, Vol.17, No. 1, Jan, pp. 48-54.

[8]. A. Nakajima, K. Oku, J. Nishidai, T. Shiraishi, Y. Ogihara, K. Mizuki, and M. Kumazava, (1988). “Development of active filter with series resonant circuit,” in Proc 19th IEEE Annu. Power Electronics Specialists Conf. Rec., Apr. 11-14, Vol. 2, pp. 1168-1173.

[9]. L. Malesani, P. Mattavelli, and P. Tomasin, (1997). “High performance hysteresis modulation technique for active filters,” IEEE Trans. Power Electron., Vol. 12, No. 5, pp. 876–884, Sep.

[10]. S. Fukuda and R. Imamura, (2005). “Application of a sinusoidal internal model to current control of three-phase utility-interface converters,” IEEE Trans. Ind. Electron., Vol. 52, No. 2, pp. 420–426, Apr.

[11]. X. Yuan, W. Merk, H. Stemmler, and J. Allmeling, (2002). “Stationary-frame generalized integrators for current control of active power filters with zero steadystate error for current harmonics of concern under unbalanced and distorted operating conditions,” IEEE Trans. Ind. Appl. Mar, Vol. 38, No. 2, pp. 523–532.

[12]. K. Nishida, Y. Konishi, and M. Nakaoka, (2002). “Current control implementation with deadbeat algorithm for three-phase current-source active power filter,” Proc. Inst. Elect. Eng., Electr. Power Appl. Jan, Vol. 149, No. 4, pp. 275–282.

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Research Paper

Fuzzy-Differential Evolution Method for Optimal Capacitor Placement in Distribution Systems

Dinakara prasad Reddy* , V. Usha Reddy**

* Student, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh, India.

** Assistant Professor, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh.

P. Dinakara Prasad Reddy and V. Usha Reddy (2011). Fuzzy-Differential Evolution Method For Optimal Capacitor Placement In Distribution Systems. i-manager’s Journal on Electrical Engineering, 4(3), 54-58. https://doi.org/10.26634/jee.4.3.1400

Abstract

This paper presents a fuzzy and Differential Evolution (DE) method for the placement of capacitors on the primary feeders of the radial distribution systems to reduce the power losses and to improve the voltage profile. Fuzzy approach is used to find the optimal capacitor locations. Differential Evolution method is used to find the sizes of the capacitors. The proposed method is tested on 10-Bus,15-Bus and 34-Bus test systems and the results are presented.

References

[1]. Ching-tzong su, chih-cheng Tsai (1996). “A new fuzzy reasoning approach to optimum capacitor allocation for primar y distribution systems”, IEEE international conference.

[2]. P.V. Prasad, S. Sivanagaraju and N.Sreenivasulu (2007). “A fuzzy – genetic algorithm for optimal capacitor placement in radial distribution systems”, ARPN Journal of Engineering and Applied Sciences, June .

[3]. K.Prakash and M.Sydulu (2007). “Particle swarm optimization based capacitor placement on radial distribution systems”, IEEE.

[4]. M. Damodar Reddy, Prof. V.C. Veera Reddy, “Optimal Capacitor Placement Using Fuzzy And Real Coded Genetic Algorithm For Maximum Savings”, Journal of Theoretical and Applied Information Technology.

[5]. S. H. Lee and J. J. Grainger, (1981). “Optimum placement of fixed and switched capacitors on primary distribution feeders”, IEEE Trans. on Power Apparatus and systems, Vol. 100, pp. 345-352, Jan.

[6]. J. J. Grainger and S. H. Lee, (1982). “Capacity release by shunt capacitor Placement on distribution feeders: A new voltage-dependent model” IEEE Trans. On Power Apparatus and Systems, May., Vol. 101, pp. 1236-1244.

[7]. Y. Baghzouz and S. Ertem, (1990). ”Shunt capacitor sizing for radial Distribution feeders with distorted substation vo Itages”, IEEE Trans. on Power Delivery, Apr. Vol. 5, pp. 650-657.

[8]. J. L Bala, P. A. Kuntz, and R. M. Taylor, (1995). “Sensitivity-based optimal capacitor placement on a radial distribution feeder”, in Proc. Northcon 95 IEEE Technical Application Conf, pp. 225-230.

[9]. S. Sundhararajan and A. Pahwa, (1994). “Optimal selection of capacitors for radial distribution systems using a genetic algorithm”, IEEE Trans. On Power Systems, Aug. Vol. 9, pp. 1499-1507.

[10]. C. T. Su, C. S. Lee, and C. S. Ho, (1999). “Optimal selection of capacitors in distribution systems”, in Proc. IEEE Power Tech Conference.

[11]. K. Y. Lee and F. F. Yang, (1998). “Optimal reactive power planning using evolutionary algorithms: A comparative study for evolutionary programming, evolutionary strategy, genetic algorithm, and linear Programming”, IEEE Trans. on Power Systems, Feb. Vol. 13, pp. 101-108.

[12]. R. Storn and K. Price, (1996). ”Minimizing the real functions of the ICEC'96 contest by differential evolution”, in Proc. IEEE on Evolutionary Computation Conf, pp. 842- 844.

[13]. K. V. Price, (I997). “Differential evolution vs. The functions of the Znd ICEO, in Proc. EEE on Evolutionary Cornputation Conf, pp.153-157.

[14]. R. Storn, (1999). “System design by onstraint adaptation and differential evolution”, IEEE Trans. Evolutionary Computation, Apr. Vol. 3, pp.22-34.

i-manager's Journal on Electrical Engineering (JEE)

Current Issue Vol. 18 Issue 1

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Volume 4 Issue 3 January - March 2011

Ananthi Kaliyamoorthy* , S. Manoharan**

* Assistant Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore. **Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore.

Ananthi Kaliyamoorthy, and S. Manoharan (2011). A Survey On Hardware And Software Optimization Of Microprocessors For Low Power Consumption. i-manager’s Journal on Electrical Engineering, 4(3), 1-9. https://doi.org/10.26634/jee.4.3.1393

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Adil Sarwar* , M.S. Jamil Asghar**

* Research Scholar, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India. ** Professor, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India.

Adil Sarwar, and M.S. Jamil Asghar (2011). A Low Cost Microcontroller Based Triggering Circuit For Multilevel Inverter. i-manager’s Journal on Electrical Engineering, 4(3), 10-16. https://doi.org/10.26634/jee.4.3.1394

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Weibo Hu * , Donald Lie**

* Research Scholar, ECE Department of Texas Tech. University, Lubbock. ** Associate Professor, ECE Department of Texas Tech. University, Lubbock.

Weibo Hu and Donald Y.C. Lie (2011). A 10-Bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method. i-manager’s Journal on Electrical Engineering, 4(3), 17-22. https://doi.org/10.26634/jee.4.3.1395

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Yash Pal* , A. Swarup**, Bhim Singh***

Yash Pal, A. Swarup and Bhim Singh (2011). A 3p-3w Upqc Integrated With Star-Hexagon Transformer For 3p-4w Distribution System. i-manager’s Journal on Electrical Engineering, 4(3), 23-31. https://doi.org/10.26634/jee.4.3.1396

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Sankar S*

Senior Lecturer, Panimalar Institute of Technology, Chennai.

S. Sankar (2011). Distribution Network Planning With Advanced Centralized Voltage Regulation System. i-manager’s Journal on Electrical Engineering, 4(3), 32-37. https://doi.org/10.26634/jee.4.3.1397

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K. Gopal* , S. Praveen**, N. Suthanthira Vanitha***

*,** BE. II-EEE, Knowledge Institute of Technology, Salem, India. *** Professor, Department of EEE, Knowledge Institute of Technology, Salem, India.

K. Gopal, S. Praveen and N. Suthanthira Vanitha (2011). Mobile Voting System Using IRIS Recognition And Cryptography Techniques. i-manager’s Journal on Electrical Engineering, 4(3), 38-42. https://doi.org/10.26634/jee.4.3.1398

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M. S. Sujatha* , T. Susritha**, Vijay Kumar***

*,** Research Scholar, Department of EEE,SVEC, A.Rangampeta, Tirupati. *** Professor, Department of EEE, JNTUCEA, Ananthpur.

M.S. Sujatha, T. Susritha and M. Vijay Kumar (2011). Adaptive Neuro-Fuzzy Dividing Frequency Control For The Development Of Hybrid Active Power Filter. i-manager’s Journal on Electrical Engineering, 4(3), 43-53. https://doi.org/10.26634/jee.4.3.1399

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Dinakara prasad Reddy* , V. Usha Reddy**

* Student, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh, India. ** Assistant Professor, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh.

P. Dinakara Prasad Reddy and V. Usha Reddy (2011). Fuzzy-Differential Evolution Method For Optimal Capacitor Placement In Distribution Systems. i-manager’s Journal on Electrical Engineering, 4(3), 54-58. https://doi.org/10.26634/jee.4.3.1400

Abstract

References

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* Assistant Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore.

**Professor, Department of Electronics and Instrumentation Engineering, Karpagam College of Engineering, Coimbatore.

* Research Scholar, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India.

** Professor, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India.

* Research Scholar, ECE Department of Texas Tech. University, Lubbock.

** Associate Professor, ECE Department of Texas Tech. University, Lubbock.

Yash Pal* , A. Swarup, Bhim Singh*

K. Gopal* , S. Praveen, N. Suthanthira Vanitha*

, BE. II-EEE, Knowledge Institute of Technology, Salem, India.

Professor, Department of EEE, Knowledge Institute of Technology, Salem, India.

M. S. Sujatha* , T. Susritha, Vijay Kumar*

, Research Scholar, Department of EEE,SVEC, A.Rangampeta, Tirupati.

Professor, Department of EEE, JNTUCEA, Ananthpur.

* Student, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh, India.

** Assistant Professor, Electrical and Electronics Engineering, S.V.U College of Engineering, Tirupati, Andhra Pradesh.