Secret Image Sharing Scheme Based on Compressed Sensing
Implementation of HOG Based Feature Extraction Method
Soldier Health and Position Monitoring System using GPS and IOT Technology
A Review on the Closed-Loop Strategy for Speed Control of BLDC Motors
V/F Based Speed Controller of Induction Motor using Ann Controller - A Review
Blockchain 3.0: Towards a Secure Ballotcoin Democracy through a Digitized Public Ledger in Developing Countries
Fetal ECG Extraction from Maternal ECG using MATLAB
Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities
Detection of Phase to Phase Faults and Identification of Faulty Phases in Series Capacitor Compensated Six Phase Transmission Line using the Norm of Wavelet Transform
A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR
A novel mathematical ECG signal analysis approach for features extraction using LabVIEW
Filtering of ECG Signal Using Adaptive and Non Adaptive Filters
Application of Polynomial Approximation Techniques for Smoothing ECG Signals
A Novel Approach to Improve the Wind Profiler Doppler Spectra Using Wavelets
Implementation of HOG Based Feature Extraction Method
The design of a compact monopole dual-band antenna suitable for dual-band applications is proposed in this research. The antenna consists of eight rectangular patches, each measuring 40 × 30 × 1.6 mm³. It is designed to operate in two frequency bands: 2.18–2.63 GHz and 7.10–7.91 GHz, with resonance frequencies at 2.4 GHz and 7.5 GHz, ensuring a return loss (S11) of less than 10 dB. The results demonstrate that the proposed antenna achieves a bandwidth of 450 MHz (2.18–2.63 GHz) and 810 MHz (7.10–7.91 GHz). This bandwidth coverage allows for the inclusion of the 2.4 GHz range required for WiMAX as well as the 7.5 GHz range suitable for short-range radar and wireless data transmission applications. The antenna is simulated using HFSS v13 software, providing an accurate and reliable analysis of its performance. The compact size of the antenna makes it suitable for integration into various wireless devices and systems, offering versatility and adaptability. Overall, the presented compact monopole dual-band antenna demonstrates its efficacy in achieving dual-band operation, covering essential frequency ranges for WiMAX, short-range radar, and wireless data transmission applications. Its compact design and wide bandwidth make it a valuable candidate for modern wireless communication systems.
The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA.
The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, which is a widely used tool for verifying digital circuits. Additionally, it aims to demonstrate the effectiveness of using the UVM methodology in verifying complex chip systems and highlights the importance of developing reliable and efficient verification methods for the VLSI industry.
The integration of an E-slot within the conventional microstrip patch antenna structure offers improved radiation characteristics and bandwidth. This research presents the design and analysis of a rectangular microstrip patch antenna with an E-slot. The proposed antenna is designed to operate at a specific frequency in the microwave range. The design process involves determining the dimensions of the rectangular patch, feedline, and E-slot to achieve the desired resonance frequency. The simulation and optimization are carried out using electromagnetic simulation software, considering the dielectric substrate properties and other relevant parameters. The E-slot is strategically placed within the patch structure to enhance the antenna's performance. It acts as an additional resonating element, contributing to increased bandwidth and improved radiation characteristics, such as gain and directivity. The integration of the E-slot modifies the current distribution on the patch, resulting in enhanced radiation properties. The performance of the proposed antenna is evaluated through various parameters, including return loss, radiation pattern, and bandwidth. Overall, the rectangular microstrip patch antenna with an E-slot presents a promising solution for achieving enhanced performance in terms of bandwidth and radiation characteristics. The proposed design opens up possibilities for further advancements in microstrip antenna technology, facilitating the development of an efficient and compact antenna structure for modern wireless applications.
The Binary Min-Redundancy Max-Diversity (BMRMD) was utilized to determine the computer network hacking and attacks. The Intrusion Detection System (IDS) is crucial for detecting attacks on an organization, which have increased in size and scale, as well as other anomalies. IDS achieves this by preparing for the unauthorized information related to network security and it is essential for distinguishing various types of attacks. The organization's traffic dataset contains numerous highlights, so selecting and eliminating irrelevant items improves the accuracy of the organization's calculations. Containing a large amount of meaningless or excessive data, a dataset can cause fitting problems and reduce the capacity of the model to learn meaningful patterns. BRMMD approach covers not only the significance of each element but also the expected accuracy when an ideal set of features is given. Solving such challenges requires a series of feature selection techniques. Therefore, the challenge is addressed by evaluating the repeatability of the features and determining their relevance to the target class based on the optimal grouping of the included features.
The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building blocks to work with codes, and it allows a dynamic approach. Simulation results show that the designed controller has a good performance and meets all the system specifications.
