Design and Verification of Memory by using UVM Methodology

Sonali Sangode*, Chandrahas Sahu**
*-** Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, Bhilai, Durg, Chhattisgarh, India.
Periodicity:January - June'2023


The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building blocks to work with codes, and it allows a dynamic approach. Simulation results show that the designed controller has a good performance and meets all the system specifications.


UVM, TestBench, Verification, VLSI, SOC Design, CMOS, DRAM, SRAM, and EEPROM.

How to Cite this Article?

Sangode, S., and Sahu, C. (2023). Design and Verification of Memory by using UVM Methodology. i-manager’s Journal on Digital Signal Processing, 11(1), 35-40.


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