Boosting Chip Verification Efficiency: UVM-Based Adder Verification with QuestaSim

Niharika Sahu*, Chandrahas Sahu**
*-** Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Bhilai, India.
Periodicity:January - June'2023


The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, which is a widely used tool for verifying digital circuits. Additionally, it aims to demonstrate the effectiveness of using the UVM methodology in verifying complex chip systems and highlights the importance of developing reliable and efficient verification methods for the VLSI industry.


System Verilog, UVM Methodology, Adder, Verification.

How to Cite this Article?

Sahu, N., and Sahu, C. (2023). Boosting Chip Verification Efficiency: UVM-Based Adder Verification with QuestaSim. i-manager’s Journal on Digital Signal Processing, 11(1), 16-21.


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