Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
This paper aims to reduce the power losses and improve system reliabilty through finding optimal number, location, and sizing of Photovoltaic Distributed Generations (PV-DG). The PV-DG is modeled as a negative load, draws reactive power from grid and injects real power to the grid. Optimum allocation of PV-DGs and their sizing is obtained by Harmony Search Algorithm (HS) and Teaching-Learning-Based Optimization (TLBO) approaches. IEEE 33-bus distribution system was successfully demonstrated by that approach. HS has proven its superiority against TLBO algorithm as it uses less DGs rating devices to enhance distribution system performance. The new contribution in this research is to optimize the number of DGs that does not operate with a given number of DGs (1 DG , 2 DG ,…..) as most of the previous works. Another contribution is to study the optimization under several loading conditions.
The global primary energy demands are increasing rapidly, which arrives at almost double the growth rate of energy consumption (Senjyu, Nakaji, Uezato, & Funabashi, 2005). An enhanced network-based control structure is essential, especially to get rid of the frequency deviations, power sharing errors, and stability concerns associated with the conservative droop control mainly in the micro grids (Jiang, Cao, Li, & Peng, 2012). One of the solutions for the issues is, to introduce renewable energy, among others PV and wind energy are clean and abundantly available in nature (Faranda & Leva, 2008). The Photovoltaic (PV) systems output power fluctuates according to the irradiation and temperature (weather conditions) (Kahrobaeian & Mohamed, 2015). Irregular PV output power results in frequency variations in the power systems, especially when the penetration is high. A photovoltaic (PV) array has nonlinear I-V (current-voltage) characteristics and its output power varies with solar insolation level, besides the ambient temperature. Only one point, called Maximum Power Point (MPP), exists on the P–V (power–voltage) curve, in which the power is maximum and the MPP fluctuates if there are changes in atmospheric conditions. The maximization of power output that takes place with greater efficiency becomes significant (Rao, Tulasiram, & Brahmaiah,2005). MPPT is the technique in use for extracting maximum power which is made available from the PV module (Subudhi & Pradhan, 2013). In this paper, a new hybrid algorithm is proposed combining the features of BFOA and Particle Swarm Optimization (PSO) for tuning PID controller, to give the better output from the solar power. PSO-BFOA based Incremental Conductance method to reduce sustained oscillations and fast searching of MPPT Computer simulations illustrate the effectiveness of the proposed approach compared to that of basic versions of PSO and BFO with FPGA. The results show that there are very good correlations between the controller parameters and the process parameters.
The main objective of this research is to design a Low power 4*4 Array Multiplier using modified GDI based full adder techniques, which consumes low power and have high speed computation compared to the CMOS technology. The modification has implemented in full adder design using GDI techniques in which the logical circuit reduces the number of transistors in the overall schematic. As we design any types of multiplier, the main logical block is adder and AND gate, similarly in this research also the authors concentrate to design Low power 4*4 Multiplier, which contains 8 full adder blocks. In these blocks, a modified GDI based full adder technology has been introduced. This way of reducing the number of transistors reduces the power consumption of overall circuits, propagation delay, and surface area. At the same time, the computation speed of the multipliers is increased.
This paper presents the concept of single phase matrix converter as an universal converter for high frequency step down operation. Matrix converter implemented as an rectifier, chopper, inverter, and cyclo-converter for a high frequency step down has been presented in this paper. This will reduce the need for the new or an extra converter requirement. The technique used for the implementation of the proposed topology was sinusoidal pulse width modulation technique. This paper verifies the four possible conversion processes, such as AC-DC, DC-DC, DC-AC, and AC-AC from a high frequency input to the desired low frequency output by the single phase matrix converter alone. The results of the four conversion topologies along with the filter has been presented in this paper. The proposed topology has been implemented in the Matlab / Simulink software and the desired results for each of the converter topology has been verified.
Reversible Logic is the dominating field of research in low power VLSI. In recent times, reversible logic has gained special attention in order to reduce power consumption mainly in concern to digital logic design. The main aim of this paper is to give an overall summary report on Digital sequential circuits like Shift registers and Counters designed using reversible logical computation. Digital circuits are the circuits implemented using Boolean logical expressions. Digital circuits find many applications in present daily life. Different types of combinational and sequential circuits are designed using reversible logic to reduce power dissipation. A Boolean function f(i1, i2, i3,……, in) having 'n' inputs and 'm' outputs is said to be logically reversible if the number of inputs are equal to the number of outputs (i.e. n = m) and the input pattern maps uniquely to the output pattern. Few reversible logic gates present in the literature are NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate, etc. The reversible gate must run both forward and backward directions such that the inputs can be retrieved with the knowledge of outputs. Reversible Logic has applications in various fields like Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI, etc. Reversible logic has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. Till date in the literature, universal shift register and shift counters are realized using reversible logical computation for the first time in this paper. In this paper, a summary report is given on Sequential circuits like Shift registers and Counters designed using reversible logical computation with improved quantum cost. A comparative study on reversible and irreversible sequential logical circuits is also given. The realized reversible logical circuits are analysed in terms of quantum cost, garbage outputs, number of gates, and propagation delay. The circuits have been designed and simulated using Xilinx software.
