Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
This monograph provides an epistemological rational for the novel discipline of “Trioinformatics”. This new logical mathematical form of expression as a methodology is an innovative way of explaining trichotomous research designs [first introduced in the i-manager’s Journal on Mathematics as a part of the Tri–Squared Test (Osler, 2012)].Trioinformatics is an in–depth way of symbolically illustrating the law of trichotomy and a mathematically–grounded rational for explaining the ternary nature of electronic circuitry. The use of Trioinformatics also adds value to investigative inquiry into the efficacy of digital instruments and tools through edu scientifically–engineered (Osler, 2013) research designs. Such research will greatly benefit from Trioinformatic logic that involves has its foundations in the tripartite aspects of nature and natural phenomena.
This paper describes the design and simulation of 1:2.1 power dividers using lumped element model at 54 MHz frequency for radar applications using ADS (Advanced Design System) software. Firstly, designing the symmetrical Wilkinson power divider (WPD) that achieves equal-power split at N arbitrary frequencies is introduced. Each quarterwave branch in the conventional Wilkinson divider is replaced by N sections of transmission lines, and the isolation between the output ports is achieved by using N resistors. The design parameters are the characteristic impedances and lengths of the N transmission line sections, and the N isolation resistors. The even–odd modes of analysis are used to derive the design equations. Closed-form expressions, which are suitable for CAD purposes, are derived for the dualband divider. This device provides maximum isolation between ports and also useful for limited bandwidth applications.
The next generation of logic gate devices is expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing MOS technology. The high electron mobility transistor (HEMT) should ideally be the best device to work for high performance VLSI circuit design. This paper enumerates the design of high speed logic gates NOR, NAND, and NOT using AlGaN/GaN high electron mobility transistor (HEMT). This high electron mobility transistor is a novel device that is projected to outperform scaled CMOS technologies. The high electron mobility transistor based devices offers high mobility, high carrier velocity for fast switching. The p-type or n-type switching behavior depends upon the polarity gate voltage. The logic gates are designed by TTL logic, so the power consumption is less in this logic gates. It can be efficiently used in VLSI ICs. PSPICE simulations have been performed on the logic gates designed using both these technologies and their output behaviors have been extensively studied at different supply voltages keeping the designs at room temperature. The performances are evaluated in terms of power, delay and PDP to show that it is possible to reduce the delay and power consumption of the logic gates by replacing the CMOS transistors of the design with the emerging high electron mobility transistor(HEMT). The simulation results of the proposed logic gates appear to have better speed of operation. It can be suitable for SPICE simulation of hybrid digital Ics.
SRAM (Static Random Access Memory) is a type of semiconductor memory that operates on a principle of Bistable Latching to store a bit of information. As the size of CMOS technology scales down to deep submicron region, power dissipation becomes a major issue in the VLSI design. The leakage power becomes dominant due to the second order effects of the transistors in deep submicron region. The leakage power aids in considerable increase of the total power dissipation of the device. The existing SRAM cells at submicron region dissipate more power and become unstable inspite of applying low power techniques like multi-threshold logic, body biasing techniques, stacked structures etc. This paper concentrates on the design of stable single ended SRAM array using power gating technique. The designs are developed and analyzed for different nm technologies using Digital Schematic and Microwind Tools. By using same tools, the Gated VDD technique based SRAM is analyzed to reduce the leakage power. The reduction in voltage swing results in reduction of dynamic power dissipation. The SRAM arrays for 2x2 and 4x4 arrays were developed using both 5T (or single ended) and Gated VDD 5T SRAM cells. The power dissipation at 90nm technology is reduced by 35% and 55.3% for gated 2x2 and 4x4 SRAM arrays respectively, when compared to single ended 2x2 and 4x4 SRAM arrays.
This paper proposes a new method based on estimation of an error by approximating the given curve into a straight line. The given curve is approximated with set of straight lines in which each straight line consists three points. In these three points, the middle point value is the arithmetic mean of first and last points. In a regular curve, the deviation between estimated point and actual point is small whereas in an irregular curve the error is large. In this paper, instantaneous current signal is taken as input and current phasor is estimated using Discrete Fourier Transform Technique. In general, many conventional methods failed during power swing due to the variations in current and voltage but the proposed method effectively detects the faults as well as power swing. Simulations are carried out in MATLAB/SIMULINK.
Leakage current has been a major issue in system on chip designs with sub-micron technologies. For 180nm and below technologies, leakage is the main factor which dominates over the dynamic power and contributes to almost or more than 40% of total power dissipation. Thus it become very important to control the leakage current. This paper presents the effect of several techniques based on leakage reduction mechanism such as stacking effect and sleepy stack transistors on standard 6-T SRAM cell. Also their comparative analysis has been carried out on the basis of leakage current, propagation delay, static noise margin (SNM) and dynamic power dissipation. The produced result depicts SRAM cell with stack technique shows 16.65%increase in propagation delay, whereas sleepy stack SRAM shows 32.83% reduction in delay as compare to basic 6T SRAM cell. When we discuss about dynamic power dissipation 6T SRAM cell with stack technique consumes 39% more, but sleepy stack cell(in sleep mode) dissipates 17.61% reduced and sleepy stack cell (in active mode)dissipates 10.47% less power as compare to basic 6T SRAM cell.
About leakage current, it can be seen that 6T SRAM cell with stacking effect shows 86% less leakage flowing through the NMOS transistor whereas in PMOS transistor the leakage current got reduced to 99.94% as compare to basic 6T SRAM cell. When we come to sleepy stack technique the leakage current flowing through the NMOS cell increases by 111%, where there is a small difference in leakage of PMOS as compare to leakage of PMOS of 6T SRAM cell. Tools Used: TANNER EDA for schematic simulation, The simulation technology used is TSMC 180nm.
