Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Validation of IOV chain using OVM Technique
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Tristate buffer is used in many applications such as electronics, communications and microprocessor circuits where they allow many devices to be connected to the same wire or bus without damage or loss of information. Contention occurs, if multiple devices are connected to same data bus. In general, digital information can be sent either serially or in parallel. For example, in microprocessor, information can be sent through data high way buses which allow multiple Tristate buffers to be connected together without loss of information. In general, buffer not only provides isolation, but also used to provide current or voltage amplification to drive heavy loads. These Tristate buffer devices can be used as bidirectional switches, because they are constructed using MOSFETS. This paper provides an energy efficient tristate buffer which is implemented using static CMOS, adiabatic and two Subthreshold adiabatic in HSPICE using 0.18μm CMOS standard process technology. The results obtained in the paper is effective in terms of power and area.
RNS based adder circuit provides an efficient way, alternate to the conventional method due to its parallel operation and small data size. The main aim for improving the performance of computation of adder is that to eliminate the carry propagation chain which is time consuming. The integers are represented in its residues of particular moduli set. The adder depends on only residues of respective moduli set. This paper presents the design of adder which is capable of providing carry free operation with proposed design of forward converter and Compressor based RNS to Binary reverse converter for the {2k -1, 2k , 2k +1}moduli set.
The floating point multiplier design is crucial for most applications like in GPUs. The designs are usually error prone. So the systems are developed to be error tolerant. The basic problem in floating point units is accuracy configuration. As accuracy plays a major role in many applications like rocket launches, the accuracy can be configured by using a log path rather than full path. Even though the error percentage increases in log path, the FP multiplier can be configured to have low power dissipation and area. The designs are developed using Verilog HDL and are functionally verified using ISIM simulator. The synthesis of the double Precision Multiplier is carried out in Xilinx ISE synthesizer and the results proved to be optimized in terms of delay and area.
This paper proposes a hybrid cascaded multilevel inverter to get a desired ac voltage from several dc voltages. These multilevel inverters are used for high power applications. These inverters give less total harmonic distortion (THD), and also can reduce the power switches when compared with conventional cascaded multilevel inverters. In general, the output of an inverter is controlled with the help of various controlling techniques. In this proposed work, these multi level inverters are controlled with modified SPWM scheme to reduce the switching losses. The objective of this paper is to evaluate the performance of an induction motor with the proposed model of fuel cell powered hybrid cascaded multilevel inverter and to control the speed of the induction motor. MATLAB/SIMULINK platform is chosen to simulate the proposed model and control technique.
As the area is shrinking with the scaling of technology, the design of SRAM memory with less leakage power becomes essential for portable devices. Due to the second order effects, the leakage power dominates the static and dynamic power at deep submicron technology. Inspite of applying low power techniques like multi-threshold logic, body biasing techniques, stacked structures etc, the existing SRAM designs at submicron region dissipate more power and become instable. This paper concentrates on low power highly stable single ended SRAM cell design using only seven transistors using Lector and Galeor based low power Techniques. Digital Schematic Tool is used to develop schematics. Microwind Tool is used to develop Layouts at different nanometer technologies. The designs are optimized for low power and good static noise margin. Also the designs are compared for submicron technologies downline from 180nm to 90nm.
