Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
A low power, low noise of the two stage neural amplifier used in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is presented. The optimization of the number of amplifier stages are discussed to achieve the minimum power and area consumption. The amplifier was submitted for fabrication in a 0.18 μm CMOS process. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μV rms and 1.90 μW respectively. The measured result shows that optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording.
Emerging countries like India, China suffer a huge problem of power crisis. The main reason for this is, power evacuation. The inability of bulk power evacuation with the present mode of transmission (HVAC & HVDC) leads us to a concept called B2B segmented AC transmission. B2B segmented AC transmission consists of a rectifier and inverter unit by using IGBT. With the advent of advanced power electronics devices, the authors are able to reduce the size and complexity of converters with increase in power ratings. By using this method the limitation of HVDC can be overcome which makes us to evacuate bulk power to longer distance with less loses. In this paper they use IGBT (Insulated Gate Bipolar Transistor) as B2B converter for transmission lines used to transmit large blocks of energy from long distance generating plants or to connect areas of large th power system. Taking a real time problem published in The New Indian Express on July 20 ,2011 which indicates power evacuation problem existing in Tamilnadu wind power sector, the authors present this paper.
Power consumed per unit switching activity in a CMOS based computational unit is greatly dependent on the power consumption of the sum and carry generation units. This paper is focussed on reducing area and PDP of the computational units through gate level and transistor level optimisation. At transistor level 6T Mux based CMOS-CPL XOR gates with stable rise and fall times are used. The concept of gate level Boolean equivalent substitution is used in optimization of logics used in carry generation in a computational unit. Optimised carry block exhibits 50% lesser delay and 45% lesser power consumption compared to a ANDOR based carry generation system. An optimized computational unit at layout level is realised with proposed logical substitutions and with Mux based XOR gates. The resulting computational unit exhibits 60% reduced power consumption compared to a standard realisation. Synthesis of layout and simulations are done by using 45nm technology.
The main objective of this paper is to design a circuit that can control the speed of a fan based on the ambient temperature. The fan is used for preventing the heat problems faced while using high graphics in a laptop or PC. The speed of the fan is varied based on the pulses that the timer sends out and the concept of pulse width modulation is used. This provides a simple and inexpensive way to protect systems like a computer from overheating. The existing external PC cooling fans have a higher energy consumption than the proposed model. This model is temperature controlled and the motor is powered on and off based on the pulsed output from the Pulse Width Modulator (PWM) generator circuit which invariably depends on the temperature. Hence the model provides cooling based on the need rather than continuously.
In almost all of the currently working circuits, especially in analog circuits implementing signal processing applications, basic arithmetic operations such as multiplication, addition, subtraction and division are performed on values which are represented by voltages or currents. However, in this paper, we propose a new and simple method for performing analog arithmetic operations, by which in this scheme, signals are represented and stored through a memristance of the newly found circuit element, i.e. memristor, instead of voltage or current. Some of these operators such as divider and multiplier are much simpler and faster than their equivalent voltage-based circuits and they require less chip area. In addition, a new circuit is designed for programming the memristance of the memristor with predetermined analog value. Presented simulation results demonstrate the effectiveness and the accuracy of the proposed circuits.
