i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 12 Issue 1

Dynamic Simulation and Sensitivity Analysis of Steam Generation Solar Power Plant
Unified Power Quality Conditioner (UPQC) Research Study on Steady - State Power Flow
Photovoltaic Module Failure Detection using Machine Vision and Lazy Learning Technique
Design and Implementation of Wallace Tree Multiplier and Its Applications in FIR Filter
Review on Obstacle Detection in Solar Panel Cleaning Applications

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Volume 8 Issue 2 July - December 2020

Research Paper

Optimization of Metal Interconnects in I/O Cells and Banks to Improve Robustness of ESD Protection Network in 16 nm FinFet Technology for Flip Chip and Wire Bond Applications

Oleg Semenov * , Ekaterina Dumalkina **

*-** NXP Semiconductors, Moscow, Russia.

Semenov, O., and Dumalkina, E. (2020). Optimization of Metal Interconnects in I/O Cells and Banks to Improve Robustness of ESD Protection Network in 16 nm FinFet Technology for Flip Chip and Wire Bond Applications. i-manager's Journal on Circuits and Systems, 8(2), 1-9. https://doi.org/10.26634/jcir.8.2.18079

Abstract

As IC technologies move forward into sub-16 nm domains, ESD protection design is rapidly becoming a big IC design challenge. Interconnects inherently forms part of any ESD protection network. Without careful and quantitative design of metal interconnects, it would not be possible to achieve robust whole-chip ESD protection circuit. Usually, a failed metal interconnect forms an connection. ESD stress results in the permanent change in the interconnects resistance and the electro migration lifetime reduction. To optimize the interconnects of ESD devices and networks, the EDA software should be used. It performs electrical simulation and is capable to analyzing the large complex metal interconnects in the standalone cells and small blocks. In this paper, we analyze and optimize the metal interconnects in standalone I/O cell and small I/O bank with respect to CDM ESD stress using simulations in the industrial EDA tool. The layouts of these cells were implemented in 16 nm FinFet technology with 9M metal stack suitable for flip chip and wire bond applications. Both GDS and CCI based flows were applied. The effect of the ESD current distribution at the contact area of the anode and cathode and its accuracy of were investigated. Finally, the recommendations for interconnects (metal frame) optimization in the I/O cells with respect to CDM ESD stress were elaborated.

References

[1]. Anderson, W. R., Eppes, D., & Beebe, S. (2009). Metal and silicon burnout failures from CDM ESD testing. In 2009, 31 st EOS/ESD Symposium (pp. 1-8). IEEE.

[2]. Bulumulla, S. B., Caggiano, M. F., Lischner, D. J., & Wolf, R. K. (2001, May). A comparison of large I/O flip chip and st wire bonded packages. In 2001, Proceedings of 51 Electronic Components and Technology Conference (Cat. No. 01CH37220) (pp. 1122-1126). IEEE. https://doi. org/10.1109/ECTC.2001.927965

[3]. Dong, Z., Lu, F., Wang, L., Ma, R., Zhang, C., Zhao, H., ... & Liaw, P. (2014, May). ESD characterization and design guidelines for interconnects in 28nm CMOS. In IEEE International Interconnect Technology Conference (pp. 99-102). IEEE. https://doi.org/10.1109/IITC.2014.6831845

[4]. Ershov, M., Feinberg, Y., Cadjan, M., Klein, D., & Etherton, M. (2013, September). EDA software for verification of metal interconnects in ESD protection th networks at chip, block, and cell level. In 2013, 35 Electrical Overstress/Electrostatic Discharge Symposium (pp. 1-7). IEEE.

[5]. Fu, G., Tang, M., Feng, Q., Bian, P., & Mao, J. (2015, December). Fast transient electro-thermal simulation of on-chip interconnects in the presence of ESD pulses. In 2015, IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) (pp. 166-169). IEEE. https://doi. org/10.1109/EDAPS.2015.7383693

[6]. Palesko, C. A., & Vardaman, E. J. (2010, June). Cost comparison for flip chip, gold wire bond, and copper wire bond packaging. In 2010, Proceedings 60th Electronic Components and Technology Conference (ECTC) (pp. 10- 13). IEEE. https://doi.org/10.1109/ECTC.2010.5490877

[7]. Freescale. (2008). Introduction to the Plastic Ball Grid Array (PBGA) [Powerpoint Presentation]. Retrieved from https://www.nxp.com/docs/en/package-information/PBG APRES.pdf

[8]. Rosenbaum, E., Shukla, V., & Keel, M. S. (2011, January). ESD protection networks for 3D integrated circuits. In 2011, IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International (pp. 1-7). IEEE. https://doi.org/10.1109/3DIC.2012.6262965

[9]. Semenov, O., Leskova, L., Gerasimova, S., & Vasiounin, D. (2018). Trends in ESD protection design for I/O libraries in advanced CMOS and FINFET technologies. i-manager's Journal on Circuits & Systems, 6(3), 1-8. https://doi.org/10. 26634/jcir.6.3.14878

[10]. Smedes, T., & Li, Y. (2003, September). ESD phenomena in interconnect structures. In 2003, Electrical Overstress/Electrostatic Discharge Symposium (pp. 1-8). IEEE.

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Research Paper

Current Mode Filters Employing Current Differencing Transconductance Amplifiers

Mustafa Konal * , Firat Kacar , Cengiz Polat Uzunoglu *

* Department of Electronics and Telecommunication Engineering, Namik Kemal University, Tekirdag, Turkey.

Department of Electrical and Electronics Engineering, Istanbul University-Cerrahpasa, Istanbul, Turkey.

* Department of Electrical and Electronics Engineering, Istanbul University-Cerrahpasa, Istanbul, Turkey.

Konal, M., Kacar, F., and Uzunoglu, C. P. (2020). Current Mode Filters Employing Current Differencing Transconductance Amplifiers. i-manager's Journal on Circuits and Systems, 8(2), 10-15. https://doi.org/10.26634/jcir.8.2.17789

Abstract

In this paper, band-pass/low-pass bi-quad filter realizations are proposed. The designed current-mode filters contain single input and two outputs based on two current differencing transconductance amplifiers (CDTAs) and only two grounded capacitors without any resistors can synchronically operate. The low-pass (LP) and the band-pass (BP) filter responses of the proposed realization are investigated. The pole angular frequency ω₀ and bandwidth ω₀/Q of the circuit are separately and electronically adjustable. Simulation results are performed with LTspice Simulator using 0.18 μm TSMC CMOS process parameters. Based on this study, simulation and theoretical results are in harmony for the proposed circuits.

References

[1]. Bang, J., Song, J., & Lee, W. (2014). Analyzing of CDTA using a new small signal equivalent circuit and application of LP filters. Journal of the Korea Academia-Industrial Cooperation Society, 15(12), 7287-7291. https://doi.org/ 10.5762/KAIS.2014.15.12.7287

[2]. Bekri, A. T., & Anday, F. (2005, September). N -order lowpass filter employing current differencing transconductance amplifiers. In Proceedings of the 2005 European Conference on Circuit Theory and Design, (Vol. 2, pp. II- 193). IEEE. https://doi.org/10.1109/ECCTD.2005.1523026

[3]. Biolek, D. (2003, September). CDTA-building block for current-mode analog signal processing. In Proceedings of the European Conference on Circuit Theory and Design (ECCTD 2003) (Vol. 3, pp. 397-400).

[4]. Biolek, D., & Biolková, V. (2006, September). Current- mode CDTA-based comparators. In The 13th Electronic Devices and Systems 2006 IMAPS CS/SK International Conference EDS (pp. 6-10).

[5]. Biolek, D., Biolkova, V., & Kolka, Z. (2009). Currentmode biquad employing single CDTA. Indian Journal of Pure and Applied Physics, 47(7), 535-537.

[6]. Biolek, D., Hancioglu, E., & Keskin, A. Ü. (2008). Highperformance current differencing transconductance amplifier and its application in precision current-mode rectification. AEU-International Journal of Electronics and Communications, 62(2), 92-96. https://doi.org/10.1016/j. aeue.2007.03.003

[7]. Biolek, D., Keskin, A. Ü., & Biolkova, V. (2010). Grounded capacitor current mode single resistance-controlled oscillator using single modified current differencing transconductance amplifier. IET Circuits, Devices & Systems, 4(6), 496-502. https://doi.org/10.1049/iet-cds. 2009.0330

[8]. Bumrongchoke, T., Duangmalai, D., & Jaikla, W. (2010, October). Current differencing transconductance amplifier based current-mode quadrature oscillator using grounded capacitors. In 2010, 10th International Symposium on Communications and Information Technologies (pp. 192-195). IEEE. https://doi.org/10.1109/ ISCIT.2010.5664834

[9]. Chien, H. C. (2017). Current-mode square wave generators based on a single CDTA. International Journal of Electronics, 104(9), 1589-1605. https://doi.org/10.1080/ 00207217.2017.1312714

[10]. Jaikla, W., Siripruchyanun, M., Bajer, J., & Biolek, D. (2008). A simple current-mode quadrature oscillator using single CDTA. Radioengineering, 17(4), 33-40.

[11]. Jin, J., & Wang, C. (2012). Single CDTA-based currentmode quadrature oscillator. AEU-International Journal of Electronics and Communications, 66(11), 933-936. https:// doi.org/10.1016/j.aeue.2012.03.018

[12]. Jin, J., & Wang, C. (2014). CDTA-based electronically tunable current-mode quadrature oscillator. International Journal of Electronics, 101(8), 1086-1095. https://doi.org/ 10.1080/00207217.2013.805394

[13]. Kacar, F., & BAŞAK, M. E. (2014). A new mixed mode full-wave rectifier realization with current differencing transconductance amplifier. Journal of Circuits, Systems, and Computers, 23(07), 1-5. https://doi.org/10.1142/S02 18126614501011

[14]. Kacar, F., & Kuntman, H. (2009, May). A new CMOS current differencing transconductance amplifier (CDTA) and its biquad filter application. In IEEE EUROCON 2009 (pp. 189-196). IEEE. https://doi.org/10.1109/EURCON. 2009.5167629

[15]. Kaçar, F., & Kuntman, H. (2010, December). Design of quadrature oscillator using Current Differencing (CDTA) Transconductance Amplifier. In National Conference on Electrical, Electronics and Computer Engineering (pp. 399-403). IEEE.

[16]. Kacar, F., & Kuntman, H. H. (2011). A new, improved CMOS realization of CDTA and its filter applications. Turkish Journal of Electrical Engineering & Computer Sciences, 19(4), 631-642. https://doi.org/10.3906/elk-1003-467

[17]. Keskin, A. Ü., & Biolek, D. (2006). Current mode quadrature oscillator using current differencing transconductance amplifiers (CDTA). IEE Proceedings - Circuits, Devices and Systems, 153(3), 214-218. https://doi.org/10.1049/ip-cds:2 0050304

[18]. Khateb, F., VÁVRA, J., & Biolek, D. (2010). A novel current-mode full-wave rectifier based on one CDTA and two diodes. Radioengineering, 19(3), 437-445.

[19]. Koton, J., Herencsar, N., Vrba, K., & Minaei, S. (2011, May). Precision full-wave current-mode rectifier using current differencing transconductance amplifier. In 2011, IEEE 3rd International Conference on Communication Software and Networks (pp. 460-463). IEEE. https://doi.org/ 10.1109/ICCSN.2011.6014935

[20]. Kumngern, M., & Dejhan, K. (2009, January). Electronically tunable current-mode quadrature oscillator using current differencing transconductance amplifiers. In TENCON 2009-2009 IEEE Region 10 Conference (pp. 1-4). IEEE. https://doi.org/10.1109/TENCON.2009.5396218

[21]. Kumngern, M., Lamun, P., & Dejhan, K. (2012). Current‐mode quadrature oscillator using current differencing transconductance amplifiers. International Journal of Electronics, 99(7), 971-986. https://doi.org/10. 1080/00207217.2011.651693

[22]. Lahiri, A. (2009a). New current-mode quadrature oscillators using CDTA. IEICE Electronics Express, 6(3), 135- 140. https://doi.org/10.1587/elex.6.135

[23]. Lahiri, A. (2009b). Novel voltage/current-mode quadrature oscillator using current differencing transconductance amplifier. Analog Integrated Circuits and Signal Processing, 61(2), 199-203. https://doi.org/10. 1007/s10470-009-9291-0

[24]. Pandey, N., & Pandey, R. (2013). Current mode fullwave rectifier based on a single MZC-CDTA. Active and Passive Electronic Components, 1-5. https://doi.org/10.11 55/2013/967057

[25]. Pandey, N., & Paul, S. K. (2011). Single CDTA-based current mode all-pass filter and its applications. Journal of Electrical and Computer Engineering, 2011, 1-5. https:// doi.org/10.1155/2011/897631

[26]. Prasad, D., Bhaskar, D. R., & Singh, A. K. (2008). Realisation of single-resistance-controlled sinusoidal oscillator: A new application of the CDTA. WSEAS Transactions on Electronics, 5(6), 257-259.

[27]. Prasad, D., Bhaskar, D. R., & Singh, A. K. (2009a). Multifunction biquad using single current differencing transconductance amplifier. Analog Integrated Circuits and Signal Processing, 61(3), 309-313. https://doi.org/10. 1007/s10470-009-9310-1

[28]. Prasad, D., Bhaskar, D. R., & Singh, A. K. (2009b). Universal current-mode biquad filter using dual output current differencing transconductance amplifier. AEUInternational Journal of Electronics and Communications, 63(6), 497-501. https://doi.org/10.1016/j.aeue.2008.02.012

[29]. Prasad, D., Bhaskar, D. R., & Singh, A. K. (2010). New grounded and floating simulated inductance circuits using current differencing transconductance amplifiers. Radioengineering, 19(1), 194-198.

[30]. Sedra, A. S., & Smith, K. C. (2003). Microelectronic circuits (5th Ed.). New York: Oxford University Press.

[31]. Shah, N. A., Quadri, M., & Iqbal, S. Z. (2008a). CDTA based transimpedance type first-order all-pass filter. WSEAS Transactions on Electronics, 5(6), 280-284.

[32]. Shah, N. A., Quadri, M., & Iqbal, S. Z. (2008b). High output impedance current-mode allpass inverse filter using CDTA. Indian Journal of Pure and Applied Physics, 46, 893- 896.

[33]. Soni, G. S., & Ansari, M. S. (2014, July). Current-mode electronically-tunable Schmitt Trigger using single 65nm±0.75 V CMOS CDTA. In 2014, International Conference on Signal Propagation and Computer Technology (ICSPCT 2014) (pp. 137-141). IEEE. https://doi. org/10.1109/ICSPCT.2014.6884939

[34]. Tangsrirat, W. (2007). Current differencing transconductance amplifier-based current-mode four-phase quadrature oscillator. Indian Journal of Enginnering and Materials Sciences, 14(4), 289-294.

[35]. Tangsrirat, W., & Tanjaroen, W. (2008). Current-mode multiphase sinusoidal oscillator using current differencing transconductance amplifiers. Circuits, Systems & Signal Processing, 27(1), 81-93. https://doi.org/10.1007/s00034-0 07-9010-y

[36]. Tangsrirat, W., Pukkalanun, T., & Surakampontorn, W. (2010). Resistorless realization of current-mode first-order allpass filter using current differencing transconductance amplifiers. Microelectronics Journal, 41(2-3), 178-183. https://doi.org/10.1016/j.mejo.2010.02.001

[37]. Tanjaroen, W., & Tangsrirat, W. (2008, May). Resistorless current-mode first-order allpass filter using CDTAs. In 2008, 5th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (Vol. 2, pp. 721-724). IEEE. https://doi.org/10.1109/ECTICON.2008.4600532

[38]. Uygur, A., & Kuntman, H. (2006a). Low-voltage current differencing transconductance amplifier in a novel allpass configuration. In MELECON 2006-2006 IEEE Mediterranean Electrotechnical Conference (pp. 23-26). IEEE. https://doi. org/10.1109/MELCON.2006.1653026

[39]. Uygur, A., & Kuntman, H. (2006b). CDTA-based quadrature oscillator design. In 2006, 14th European Signal Processing Conference (pp. 1-4). IEEE.

[40]. Yildirim, M., Ugranli, H. G., & Kaçar, F. (2016). Low voltage low power DTMOS-CDTA filter design using for biomedical signal processing applications. International Journal of Computational and Experimental Science and Engineering, 2(2), 6-9.

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Research Paper

Dynamical Behavior of a Van der Pol Oscillator Circuit with Internal Delay

Saumen Chakraborty* , Saumendra Sankar De Sarkar **

* Department of Physics, Bidhan Chandra College, Asansol, West Bengal, India.

** Department of Physics, Raniganj Girls' College, Raniganj, West Bengal, India.

Chakraborty, S., and Sarkar, S. S. D. (2020). Dynamical Behavior of a Van der Pol Oscillator Circuit with Internal Delay. i-manager's Journal on Circuits and Systems, 8(2), 16-21. https://doi.org/10.26634/jcir.8.2.18161

Abstract

The qualitative dynamical behavior of an electronic oscillator based on Van der Pol equation is studied with an inherent delay attributed due to finite propagation time and processing time of signal. The stability governing equations have been obtained analytically. In addition to this, the dynamics of the system has been simulated numerically. Though the inherent delay is generally small, the study has been extended for higher values of delay also. Numerical simulation results are found to be consistent with the analytical predictions. The behavior of the modified system beyond the stable region has also been explored using nonlinear tool like bifurcation diagram and chaotic behavior has been found with proper parameter values.

References

[1]. Atay, F. M. (1998). Van der Pol's oscillator under delayed feedback. Journal of Sound and Vibration, 218(2), 333- 339.

[2]. Calzolari, P. U., Franchi, E., & Soncini, G. (1992). An analytical investigation on the propagation delay in ring oscillators. Integration, 13(2), 129-152. https://doi.org/10. 1016/0167-9260(92)90002-G

[3]. Franklin, G. F., Powell, J. D., & Emami-Naeini, A. (1994). Feedback control of dynamic systems (3rd ed.). MA: Addison Wiley.

[4]. Harb, B. (2014). Effect of time delay on the pull-in range of phase locked loops. Journal of Vibroengineering, 16(1), 369-377.

[5]. Hunt, D., Korniss, G., & Szymanski, B. K. (2011). The impact of competing time delays in coupled stochastic systems. Physics Letters A, 375(5), 880-885.

[6]. Kiss, G., & Lessard, J. P. (2017). Rapidly and slowly oscillating periodic solutions of a delayed van der Pol oscillator. Journal of Dynamics and Differential Equations, 29(4), 1233-1257. https://doi.org/10.1007/s10884-017-95 99-x

[7]. Peng, M., Zhang, Z., Qu, Z., & Bi, Q. (2019). Qualitative analysis in a delayed Van del Pol oscillator. Physica A: Statistical Mechanics and its Applications, 544, 1-22. https://doi.org/10.1016/j.physa.2019.123482

[8]. Premraj, D., Suresh, K., & Thamilmaran, K. (2019). Effect of processing delay on bifurcation delay in a network of slow-fast oscillators. Chaos: An Interdisciplinary Journal of Nonlinear Science, 29(12). https://doi.org/10.1063/1.512 3417

[9]. Xu, J., & Chung, K. W. (2003). Effects of time delayed position feedback on a van der Pol–Duffing oscillator. Physica D: Nonlinear Phenomena, 180(1-2), 17-39. https:// doi.org/10.1016/S0167-2789(03)00049-6

[10]. Yao, C., He, Z., & Zou, W. (2020). Oscillation behavior driven by processing delay in diffusively coupled inactive systems: Cluster synchronization and multistability. Chaos: An Interdisciplinary Journal of Nonlinear Science, 30(12). https://doi.org/10.1063/5.0025958

[11]. Zduniak, B., Bodnar, M., & Forys, U. (2014). A modified van der Pol equation with delay in a description of the heart action. International Journal of Applied Mathematics and Computer Science, 24(4), 853-863.

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Research Paper

Low Power Radiation Hardened SRAM Cells

V. Seetha* , P. Deepa **

*-** Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, India.

Seetha, V., and Deepa, P. (2020). Low Power Radiation Hardened SRAM Cells. i-manager's Journal on Circuits and Systems, 8(2), 22-28. https://doi.org/10.26634/jcir.8.2.18091

Abstract

This paper presents low power radiation hardened cells. In this paper, two designs are proposed namely Interleaving Stacked Cell 12T (ILS 12T) and Radiation Hardened by Design 14T (RHBD 14T) SRAM cell design, in order to make the cell tolerant to single event upset and partially tolerant to double node upset. The new designed SRAM cell is ineffective to both 0-1 and 1-0 upset. The simulation software Cadence Virtuoso simulation tool is employed and it analysed a reduction in power.

References

[1]. Atias, L., Teman, A., Giterman, R., Meinerzhagen, P., & Fish, A. (2016). A low-voltage radiation-hardened 13T SRAM bitcell for ultralow power space applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2622-2633. https://doi.org/10.1109/TVLSI.2016.2518 220

[2]. Bhaskar, A. (2017, April). Design and analysis of low power SRAM cells. In 2017, Innovations in Power and Advanced Computing Technologies (i-PACT) (pp. 1-5). IEEE. https://doi.org/10.1109/IPACT.2017.8244888

[3]. Guo, J., Xiao, L., & Mao, Z. (2014). Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 1994-2001. https://doi. org/10.1109/TCSI.2014.2304658

[4]. Han, Y., Cheng, X., Han, J., & Zeng, X. (2020). Radiation-hardened 0.3–0.9-V voltage-scalable 14T SRAM and peripheral circuit in 28-nm technology for space applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(4), 1089-1093. https://doi.org/ 10.1109/TVLSI.2019.2961736

[5]. Jahinuzzaman, S. M., Rennie, D. J., & Sachdev, M. (2009). A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Transactions on Nuclear Science, 56(6), 3768-3773. https://doi.org/10.1109/TNS.2009.2032 090

[6]. Jung, I. S., Kim, Y. B., & Lombardi, F. (2012, August). A novel sort error hardened 10T SRAM cells for low voltage operation. In 2012, IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 714- 717). IEEE. https://doi.org/10.1109/MWSCAS.2012.6292120

[7]. Narasimham, B., Wang, J. K., Vedula, N., Gupta, S., Bartz, B., Monzel, C., ... & Reed, R. A. (2015, April). Influence of supply voltage on the multi-cell upset soft error sensitivity of dual-and triple-well 28 nm CMOS SRAMs. In 2015, IEEE International Reliability Physics Symposium (pp. 2C-4). IEEE. https://doi.org/10.1109/IRPS.2015.7112679

[8]. Peng, C., Huang, J., Liu, C., Zhao, Q., Xiao, S., Wu, X., ... & Zeng, X. (2018). Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 407-415. https://doi.org/10.1109/TVLSI. 2018.2879341

[9]. Qi, C., Xiao, L., Wang, T., Li, J., & Li, L. (2016). A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets. IEEE Transactions on Device and Materials Reliability, 16(3), 388-395. https:// doi.org/10.1109/TDMR.2016.2593590

[10]. Rajaei, R., Asgari, B., Tabandeh, M., & Fazeli, M. (2015). Design of robust SRAM cells against single-event multiple effects for nanometer technologies. IEEE Transactions on Device and Materials Reliability, 15(3), 429-436. https://doi.org/10.1109/TDMR.2015.2456832

[11]. Singariya, V., & Mishra, D. K. (2014). Comparison of various n-T SRAM cell fot improvement of power, speed and SNM. International Journal of Digital Application & Contemporary Research, 2(12), 1-6.

[12]. Wang, H. B., Bi, J. S., Li, M. L., Chen, L., Liu, R., Li, Y. Q., ... & Guo, G. (2014). An area efficient SEU-tolerant latch design. IEEE Transactions on Nuclear Science, 61(6), 3660- 3666. https://doi.org/10.1109/TNS.2014.2361514

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Research Paper

Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory

Pavithra S.* , P. Deepa **

*-** Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, India.

Pavithra, S., and Deepa, P. (2020). Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory. i-manager's Journal on Circuits and Systems, 8(2), 29-35. https://doi.org/10.26634/jcir.8.2.18087

Abstract

This paper presents a design for Gate-based ternary content-addressable memory (G-TCAM), utilizing G-AETCAM cells, which yields the location of given input information. The G-AETCAM cells utilizes flip-flop as memory component and control rationale hardware comprising of rationale entryways. One G-AETCAM cell encodes the input and put away the output into one encoded bit which brings about a match-line subsequent to passing from the input. G-AETCAM architecture is area efficient in terms of transistor count and speed of operations is high than the available TCAM architectures. The cascaded G-AETCAM cells are divided as banks, by considering each row as single bank of whole memory. The decoder logic used for memory design is modified by using reversible logic gate technique. Here, HL gate has been used instead of Line Decoder

References

[1]. Ahmed, A., Park, K., & Baeg, S. (2016). Resourceefficient SRAM-based ternary content addressable memory. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1583-1587. https://doi.org/10.1109/ TVLSI.2016.2636294

[2]. Hellkamp, D., & Nepal, K. (2018). True 3-valued ternary content addressable memory cell based on ambipolar carbon nanotube transistors. Journal of Circuits, Systems, and Computers, 28(5). https://doi.org/10.1142/S0218126 619500853

[3]. Irfan, M., & Ullah, Z. (2017). G-AETCAM: Gate-based area-efficient ternary content-addressable memory on FPGA. IEEE Access, 5, 20785-20790. https://doi.org/10.11 09/ACCESS.2017.2756702

[4]. Irfan, M., Ullah, Z., & Cheung, R. C. (2019). D-TCAM: A high-performance distributed RAM based TCAM architecture on FPGAs. IEEE Access, 7, 96060-96069. https:// doi.org/10.1109/ACCESS.2019.2927108

[5]. Irfan, M., Ullah, Z., Chowdhury, M. H., & Cheung, R. C. (2020). RPE-TCAM: Reconfigurable power-efficient ternary content-addressable memory on FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(8), 1925- 1929. https://doi.org/10.1109/TVLSI.2020.2993168

[6]. Junsangsri, P., Lombardi, F., & Han, J. (2015, May). A ternary content addressable cell using a single phase change memory (PCM). In Proceedings of the 25th Edition on Great Lakes Symposium on VLSI (pp. 259-264). https:// doi.org/10.1145/2742060.2742062

[7]. Karam, R., Puri, R., Ghosh, S., & Bhunia, S. (2015). Emerging trends in design and applications of memorybased computing and content-addressable memories. Proceedings of the IEEE, 103(8), 1311-1330. https://doi. org/10.1109/JPROC.2015.2434888

[8]. Reddy, V. R. K., Rao, V. V., Sailaja, M., Karthik, C., & Narendra, E. (2018). Realization of effective reversible decoder based combinational circuits. International Journal of Pure and Applied Mathematics, 120(6), 4503- 4517.

[9]. Syed, F., Ullah, Z., & Jaiswal, M. K. (2017). Fast content updating algorithm for an SRAM-based TCAM on FPGA. IEEE Embedded Systems Letters, 10(3), 73-76. https://doi.org/ 10.1109/LES.2017.2770225

[10]. Ullah, I., Ullah, Z., & Lee, J. A. (2018). Ee-tcam: An energy-efficient sram-based tcam on fpga. Electronics, 7(9), 186. https://doi.org/10.3390/electronics7090186

[11]. Ullah, I., Ullah, Z., Afzaal, U., & Lee, J. A. (2019). DURE: An energy-and resource-efficient TCAM architecture for FPGAs with dynamic updates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(6), 1298-1307. https://doi.org/10.1109/TVLSI.2019.2904105

[12]. Ullah, Z., Jaiswal, M. K., Cheung, R. C., & So, H. K. (2015, November). UE-TCAM: An ultra efficient SRAM-based TCAM. In TENCON 2015-2015 IEEE Region 10 Conference (pp. 1-6). IEEE. https://doi.org/10.1109/TENCON.2015.737 2837

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Volume 8 Issue 2 July - December 2020

Optimization of Metal Interconnects in I/O Cells and Banks to Improve Robustness of ESD Protection Network in 16 nm FinFet Technology for Flip Chip and Wire Bond Applications

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*-** NXP Semiconductors, Moscow, Russia.

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Current Mode Filters Employing Current Differencing Transconductance Amplifiers

Mustafa Konal * , Firat Kacar **, Cengiz Polat Uzunoglu ***

Konal, M., Kacar, F., and Uzunoglu, C. P. (2020). Current Mode Filters Employing Current Differencing Transconductance Amplifiers. i-manager's Journal on Circuits and Systems, 8(2), 10-15. https://doi.org/10.26634/jcir.8.2.17789

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Dynamical Behavior of a Van der Pol Oscillator Circuit with Internal Delay

Saumen Chakraborty* , Saumendra Sankar De Sarkar **

* Department of Physics, Bidhan Chandra College, Asansol, West Bengal, India. ** Department of Physics, Raniganj Girls' College, Raniganj, West Bengal, India.

Chakraborty, S., and Sarkar, S. S. D. (2020). Dynamical Behavior of a Van der Pol Oscillator Circuit with Internal Delay. i-manager's Journal on Circuits and Systems, 8(2), 16-21. https://doi.org/10.26634/jcir.8.2.18161

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Low Power Radiation Hardened SRAM Cells

V. Seetha* , P. Deepa **

*-** Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, India.

Seetha, V., and Deepa, P. (2020). Low Power Radiation Hardened SRAM Cells. i-manager's Journal on Circuits and Systems, 8(2), 22-28. https://doi.org/10.26634/jcir.8.2.18091

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Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory

Pavithra S.* , P. Deepa **

*-** Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, India.

Pavithra, S., and Deepa, P. (2020). Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory. i-manager's Journal on Circuits and Systems, 8(2), 29-35. https://doi.org/10.26634/jcir.8.2.18087

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Mustafa Konal * , Firat Kacar , Cengiz Polat Uzunoglu *

* Department of Physics, Bidhan Chandra College, Asansol, West Bengal, India.

** Department of Physics, Raniganj Girls' College, Raniganj, West Bengal, India.