i-manager's Journal on Electronics Engineering (JELE)


Volume 6 Issue 1 September - November 2015

Research Paper

Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post HocProbability Confirmatory Data Analysis Assurance ModelDesigned to Determine the Validity, Viability, andVerifiability of E–Learning Hypotheses

James Edward Osler II*
Faculty member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.
Osler, J. E., II. (2015). Trichotomous Bayes Factor Analysis [Tri–BFA]: A Post Hoc Probability Confirmatory Data Analysis Assurance Model Designed to Determine the Validity, Viability, and Verifiability of E–Learning Hypotheses. i-manager's Journal on Electronics Engineering, 6(1), 1-12. https://doi.org/10.26634/jele.6.1.3680

Abstract

This paper presents meticulous knowledge about ‘Tri–Factor Analysis: A Model and Statistical Test of Performance, Efficacy, and Content for Electronics and Digital Learning Ecosystems’. This narrative provides an epistemological rational for the use of Bayesian probability statistical testing models for E–Learning via the Tri–Squared Test and subsequent TRINOVA Post Hoc test methodology. TRINOVA is an in–depth [Trichotomous Nomographical Variance] statistical procedure for the internal testing of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. Tri–Bayes Factor Analysis (or “Tri–BFA”) is an advanced statistical measure that is designed to check the validity and reliability of a Tri–Squared Test hypothesis using Bayesian probability. This is a novel approach to advanced statistical post hoc Tri–Squared hypothesis testing. It adds merit and considerable value to the mixed methods approach of research design that involves the holistic combination and comparison of qualitative and quantitative data outcomes. A sequential series of steps using the Tri–Squared Test, TRINOVA, and Tri–BFA mathematical models are provided to illustrate the entire process of advanced statistical Trichotomous inquiry.

Research Paper

Aging Aware Radix-4 Booth Multiplier WithAdaptive Hold Logic and Razor Flip Flop

SUVARNA* , K.Rajesh**, S.Veerakumar***
* PG Scholar, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.
**_*** Assistant Professor, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.
Suvarna, S., Rajesh, K. and Veerakumar, S. (2015). Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop. i-manager's Journal on Electronics Engineering, 6(1), 13-20. https://doi.org/10.26634/jele.6.1.3681

Abstract

Digital multipliers are most efficiently used in many applications such as Fourier Transform, Discrete Cosine Transforms, and Digital Filtering for high speed and low power consumption. The throughput of the multipliers is based on speed of the multiplier, and if it is too slow then, the entire performance of the circuit will be diminished. The pMOS transistor in negative bias cause Negative Bias Temperature Instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause Positive Bias Temperature Instability (PBTI). These effects reduce the transistor speed and the system may fail due to timing violations. So here, a new multiplier was designed with novel Adaptive Hold Logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), it is possible to reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

Research Paper

OTRA Based Precision Rectifier

Rashika Anurag* , Neeta Pandey**, Rajeshwari Pandey***, Ritu Vijay****
* Associate Professor, Department of Electronics and Communication Engineering, JSS Academy of Technical Education, Uttar Pradesh, India.
**_*** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.
**** Associate Professor, Department of Electronics, Banasthali University, Rajasthan, India.
Anurag, R.,Pandey, N.,Pandey, R., and Vijay, R. (2015). OTRA Based Precision Rectifier. i-manager's Journal on Electronics Engineering, 6(1), 21-27. https://doi.org/10.26634/jele.6.1.3682

Abstract

Analog integrated circuit design is receiving a tremendous boost due to the development and application of Current- Mode (CM) processing. Application of CM techniques provides wider bandwidth; which is virtually independent of the closed loop gain, greater linearity and large dynamic range. The Operational Transresistance Amplifier (OTRA) has emerged as an effective alternate current mode analog building block. It is a high gain current input, voltage output amplifier and also free from parasitic input capacitances and resistances as its input terminals are virtually grounded thus eliminating response limitations due to parasitics. OTRA is used as an analog building block for realizing a number of circuits having applications in signal processing and generation. Precise rectification is an important requirement in instrumentation and measurement circuits and is addressed in this paper. Traditionally, diodes are used to build rectifiers however; rectification is not permitted below a voltage of ∼ 0.7 V for silicon and ∼ 0.3 V for germanium diodes due to cutin voltage. For low voltage applications, Operational Amplifiers (OPAMP) with diode connected in feedback is used which prevents the fast switching of the diodes in high frequency range due to slew rate limitation of OPAMP. This paper aims at presenting an OTRA based FWR which is suitable for low voltage rectification. The functionality of the proposed circuit is validated through SPICE simulation for which OTRA is realized using Current Feedback Operational Amplifier (CFOA).The simulation results are found in close agreement to the theoretical results.

Research Paper

A Novel Method to Eliminate Selective Harmonicsin a Multilevel Inverter

Nimain Charan Nayak*
Professor, Department of Electrical and Electronics Engineering , MNM Jain Engineering College, Chennai, India.
Nayak, N.C. (2015). A Novel Method to Eliminate Selective Harmonics in a Multilevel Inverter . i-manager's Journal on Electronics Engineering, 6(1), 28-40. https://doi.org/10.26634/jele.6.1.3683

Abstract

This paper deals with the harmonic elimination in multilevel inverters. Multilevel inverters are advanced types of inverters. The desired level of levels is obtained by using the method of triggering. A seven level cascaded H-bridge inverter has been used here. To synthesize multilevel output AC voltage using different levels of DC input, semiconductor devices must be switched on and off. The output contains harmonic and total harmonic distortion. These affect the solution and hence have to be eliminated. Selective harmonic elimination is the method in which the author selects the harmonics which needs to be eliminated. Different methods are used to eliminate the harmonics. In this paper, the author makes use of genetic algorithm to eliminate the harmonics. Genetic algorithm is a computational algorithm that solves optimization problem by imitating the genetic processes and the theory of evolution. It imitates biological evolution by using parameters such as reproduction, crossover mutation etc. The fitness function of multilevel inverters is solved and firing angles are obtained. These firing angles are obtained to the semiconductor devices and output with minimum harmonics and total harmonic distortions are obtained.

Research Paper

Study of Electromagnetic Interference

M. Satish Kumar* , A. Jhansi Rani**
* Assistant Professor, Department of Electronics and Communication Engineering, Sri Vasavi Engineering College, Tadepalligudem, India.
** Professor, Department of Electronics and Communication Engineering, V. R. Siddhardha Engineering College, Vijayawada, India.
Kumar, M.S., and Rani, A.J. (2015). Study of Electromagnetic Interference. i-manager's Journal on Electronics Engineering, 6(1), 41-46. https://doi.org/10.26634/jele.6.1.3684

Abstract

The life on Earth has been adapted to survive in an environment of natural low-frequency Electromagnetic (EM) fields in addition to the Earth's Static Geo-Magnetic field. Natural EM fields of low frequency come from two main sources, the sun and thunderstorm activity. However, fields produced by various Electrical and Electronic Systems such as Radio and Television broadcast stations, Communication Transmitters etc., and Automobile Ignition systems, Industrial Control Equipment radiate Electromagnetic Energy at much higher intensities during their normal operation. The electromagnetic environment created by these Intentional and Unintentional sources with a very different Spectral Distribution has altered this natural EM background. The electromagnetic environment created by these Intentional and Unintentional sources, when sufficiently strong, Interferes with the operation of many electrical and electronics equipment and systems which degrades the performance of the system. So the study of Electromagnetic Fields which becomes an interference to the Systems’ operation is needed. For analysis of EM fields, simulation of Co-Axial cable using CST is considered [4].