Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement

Sergey Kuznetsov*, Andrey Malkov**, Evgeny Shevchenko***, Sergey Somov****
Ph.D Student of Moscow Institute of Electronic Technology (MIET), Intern of I/O Library Design Team, NXP Semiconductors Moscow, Russia
Chief I/O Design Architect of NXP Semiconductors Moscow, Russia
Ph.D of Engineering Sciences, I/O Library Design Team Manager of NXP Semiconductors Moscow, Russia
Design Enablement NXP Semiconductors Moscow Site Manager, Russia
Periodicity:December - February'2018


In this paper the problem of reducing difference between rise and fall delays (output delay skew) of I/O cells and duty cycle enhancement to meet 2.5V RGMII 2.0 interface I/Os timing requirements at Gigabit Ethernet 125MHz clock speed [5] was investigated and analyzed. Stacked I/O design specifics (reference voltages and their instability) were considered for example design of 2.5V I/Os in 28nm technology with 1.8V dgo transistors [10]. Testbench for test I/O bank LPE netlist spice simulations was created in Cadence Virtuoso design environment for I/O rise/fall delays and duty cycle evaluation at bank-level including package R-L-C and T-line models, and worst data toggle patterns were used to take simultaneously switching effects into account. Method of connecting decoupling capacitors to reference voltages was used to achieve reduced voltage noise, adjusted rise/fall delays, reduced skew, and output signal stabilized for both single I/O and I/O bank. Analysis was carried out for various values of decoupling capacitors to calculate appropriate one and meet given RGMII specification timing requirements.


RGMII Interface, Gigabit Ethernet, Stacked Input/Output Cell, I/O bank, SSO, Decoupling Capacitors, Timing, Duty Cycle, Rise/Fall Delay Skew, Data Toggle Pattern, Cadence.

How to Cite this Article?

Kuznetsov. S., Malkov. A., Shevchenko. E and Somov. S (2018). Method of 2.5 V Rgmii Interface I/O Duty Cycle and Delay Skew Enhancement. i-manager's Journal on Electronics Engineering, 8(2), 1-5.


[1]. Chen, H. H., Neely, J. S., Wang, M. F., & Co, G. (2003, September). On-chip decoupling capacitor optimization for noise and leakage reduction. In Integrated Circuits th and Systems Design, 2003. SBCCI 2003. Proceedings. 16 Symposium on (pp. 251-255). IEEE.
[2]. Ingels, M., & Steyaert, M. S. (1997). Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's. IEEE Journal of Solid-State Circuits, 32(7), 1136-1141.
[3]. Jou, S. J., Cheng, W. C., & Lin, Y. T. (2001). Simultaneous switching noise analysis and low-bounce buffer design. IEE Proceedings-Circuits, Devices and Systems, 148(6), 303-311.
[4]. NXP Semiconductors i.MX 8 Series Applications Processors Datasheet at microcontrollers-and-processors/arm-based-processorsa nd-mcus/ applications - processors/ 8 - processors:IMX8-SERIES.
[5]. Reduced Gigabit Media Independent Interface (RGMII) Specification, 4/1/2002. Version 2.0.
[6]. Singh, G. (1998, September). A high speed 3.3 V IO buffer with 1.9 V tolerant CMOS process. In Solid-State Circuits Conference, 1998. ESSCIRC'98. Proceedings of th the 24 European (pp. 128-131). IEEE.
[7]. Tang, K. T., & Friedman, E. G. (2002). Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), 487-493.
[8]. Tripathi, J. N., Damle, P., & Malik, R. (2017, May). Minimizing core supply noise in a power delivery network by optimization of decoupling capacitors using simulated annealing. In Signal and Power Integrity (SPI), 2017 IEEE st 21 Workshop on (pp. 1-3). IEEE.
[9]. Vazgen, S. M., Karo, H. S., Avetisyan, V. A., & Hakhverdyan, A. T. (2017, April). On-chip decoupling capacitor optimization technique. In Electronics and th Nanotechnology (ELNANO), 2017 IEEE 37 International Conference on (pp. 116-118). IEEE.
[10]. Yoshida, J. (2017). “NXP Goes All In on FD-SOI”, EE Times journal paper . Retrieved from 85

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

If you have access to this article please login to view the article or kindly login to purchase the article
Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.