In this paper the problem of reducing difference between rise and fall delays (output delay skew) of I/O cells and duty cycle enhancement to meet 2.5V RGMII 2.0 interface I/Os timing requirements at Gigabit Ethernet 125MHz clock speed  was investigated and analyzed. Stacked I/O design specifics (reference voltages and their instability) were considered for example design of 2.5V I/Os in 28nm technology with 1.8V dgo transistors . Testbench for test I/O bank LPE netlist spice simulations was created in Cadence Virtuoso design environment for I/O rise/fall delays and duty cycle evaluation at bank-level including package R-L-C and T-line models, and worst data toggle patterns were used to take simultaneously switching effects into account. Method of connecting decoupling capacitors to reference voltages was used to achieve reduced voltage noise, adjusted rise/fall delays, reduced skew, and output signal stabilized for both single I/O and I/O bank. Analysis was carried out for various values of decoupling capacitors to calculate appropriate one and meet given RGMII specification timing requirements.