i-manager's Journal on Digital Signal Processing (JDP)


Volume 7 Issue 2 April - June 2019

Research Paper

Development of Fall Detection Algorithm for Telemonitoring System

C. A. Mebrim* , O. C. Ubadike**, A. M. Aibinu***, I. I. Alegbeleye****, A. J. Onumanyi*****
* Department of Telecommunication Engineering, Federal University of Technology, Minna, Niger State, Nigeria.
** Air Force Institute of Technology, Kaduna, Kaduna State, Nigeria.
*** Department of Mechatronics Engineering, Federal University of Technology, Minna, Niger State, Nigeria.
**** Department of Computer Engineering, Federal University of Technology, Minna, Nigeria.
***** University of Pretoria, South Africa.
Mebrim, C. A., Ubadike, O. C., Aibinu, A. M., Alegbeleye. I. I., and Onumanyi, A. J. (2019). Development of Fall Detection Algorithm for Telemonitoring System. i-manager’s Journal on Digital Signal Processing. 7(2), 1-9. https://doi.org/10.26634/jdp.7.2.15942

Abstract

Fall related injuries have become the leading cause of death and hospitalization of the elderly. Most death happen when the fall of a senior citizen is found beyond the critical stage, while they live in isolation. The main approach of this work is expected to aid the senior citizens take care of the Activities of the Daily Living (ADL), thus increasing independence even in old age. The use of accelerometer was found to be suitable for effective fall detection owing to its numerous advantages. Senior citizen movement pattern is acquired at a pre-determined rate. The acquired data is preprocessed before the application of static threshold and Time delay. The threshold value is used to detect elderly fall and this is then transmitted to the care-giver via telemonitoring system. In event of a fall, the Global System for Mobile Communication (GSM) Module (incorporated in the system) sends a Short Message Service (SMS) to remote mobile phone seeking for immediate attention from the care giver. For seamless communication, the Arduino Uno was used to aid interaction between these modules. Accuracy near 100 percent was achieved with simple static threshold and time delay in this system.

Research Paper

Analysis of QRS Peak and Edge Detection in ECG Signal Using Entropy

Lokesh S.* , Udhayakumar G.**
* Department of Electronics and Communication Engineering, Vel Tech, Chennai, Tamil Nadu, India.
** Department of Electrical and Electronics Engineering, SRM Valliammai Engineering College, Kanchipuram, Tamil Nadu, India.
Lokesh. S., & Udhayakumar, G . (2019). Analysis of QRS Peak and Edge Detection in ECG Signal using Entropy. i-manager’s Journal on Digital Signal Processing. 7(2), 10-14. https://doi.org/10.26634/jdp.7.2.16830

Abstract

Electrocardiogram (ECG) is the most vital and widely used methodology to check the cardiovascular diseases. For identifying arrhythmia classification, it needs large storage space and intensive manual effort. The conventional technique of visual analysis to examine the ECG signals by doctors or physicians is not effective and time consuming. In this work, an attempt has been made towards the development of an automated system for investigation of QRS wave in ECG signals using Entropy and Edge detection. The Peak detection process starts only when the enhanced signal exceeds the preset average threshold. Conventional ECG signals are used from MIT/BIH arrhythmia database for this study. The ECG signals are processed using edge based detection and related to Pan-Tompkins algorithm for extracting the QRS features using Entropy threshold of edge detection operators. The results show that the proposed system has a sensitivity of 99.2% and accuracy values of 98.11% and a positive prediction of 98.9% using Prewitt based edge detection.

Research Paper

FPGA Implementation of Radix-2 FFT Processor Based on CORDIC Algorithm for Electromyography

Anju M. I.* , J. Mohan **, Beena M. I.***
* Department of Electronics and Communication Engineering, New Prince College of Engineering and Technology, Chennai, Tamil Nadu, India.
** Department of Electronics and Communication Engineering, SRM Valliammai College of Engineering, Chennai, Tamil Nadu, India.
*** Department of Mathematics, Ezuthachan College of Pharmaceutical Sciences, Thiruvananthapuram, Kerala, India.
Anju, M. I., Mohan, J., and Beena, M. I. (2019). FPGA Implementation of Radix-2 FFT Processor Based on Cordic Algorithm for Electromyography. i-manager’s Journal on Digital Signal Processing. 7(2), 15-24. https://doi.org/10.26634/jdp.7.2.16828

Abstract

Electromyography (EMG) is a diagnostic technique for determining the health status of the muscles and the motor neurons that regulate them. It transmits electrical signals that cause muscles to contract and relax. An EMG translates these signals into graphs or numbers and help the doctors to make diagnosis. The electric signal transmitted by the muscles will have lot of noises. Fast Fourier Transform is one of the most used algorithms for calculating the Discrete Fourier Transform (DFT). It's because of its reduction in computing time and better efficiency. A radix-2 FFT allows to analyze dynamic signals coming through muscle contractions efficiently and same can be precisely implemented using radix-4 Coordinate Rotation Digital Computer (CORDIC) algorithm. Here it deals with the calculation of muscle fatigue using EMG and proposes an ideal FFT core implementation using CORDIC algorithm as a solution for the same.

Research Paper

Novel Error Detection and Correction in Memory System using Hybrid Technology

Srimathi* , K. Balamurugan**, M. Sridevi Maheswari***
*-***Department of Electronics and Communication Engineering , Einstein College of Engineering, Tirunelveli, Tamil Nadu, India.
Srimathi., Balamurugan, K., and Maheswari, S. M. (2019). Novel Error Detection and Correction in Memory System using Hybrid Technology. i-manager’s Journal on Digital Signal Processing. 7(2), 25-32. https://doi.org/10.26634/jdp.7.2.16279

Abstract

Very Large Scale Integration (VLSI) is the science of integrating millions of transistors in a silicon chip. It is a term describing semiconductor integrated circuits composed of thousands of logic elements of memory cells. Error that occurs during the write and read operations in memory cells is a drawback for the memory ICs. Error detection and error correction plays a vital role in VLSI design by increasing the accuracy and performance of the desired circuits. Depending on the properties of the system, the channel coding can use either Automatic Repeat Request or Forward Error Correction technique in which the error correcting is introduced. In this work two techniques are used i.e. Reed Solomon code and Bose–Chaudhuri–Hocquenghem (BCH) code, where Reed Solomon code is a error detection technique which is mainly used for its possibility to adjust block length and symbol size. BCH code is a error correction technique, it is used because of its easy implementation. These two techniques are implemented in the memory cells and the performance metrics such as block length, minimum distance are calculated. From the VHDL simulation result, it is proved that BCH code is better than Reed Solomon code for the memory cells of the ICs.

Research Paper

Convolution Techniques using Modified Booth Multiplication

A. Sai Vardhan* , M. Bharathi**, N. Padmaja***
*-*** Department of Electronics and Communications Engineering, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.
Vardhan, A., Bharathi, M., and Padmaja, N. (2019). Convolution Techniques using Modified Booth Multiplication. i-manager’s Journal on Digital Signal Processing. , 7(2), 33-39. https://doi.org/10.26634/jdp.7.2.16697

Abstract

Very Large Scale Integration (VLSI) incorporates the Fixed and Floating point DSP Processors RISC based DSP Processor, ASIC based DSP processors, Computerized control frameworks, Broadcast communications, Discourse and Sound preparing for audiology and DSP Applications. The most recent investigation into about in VLSI is the design and application of the DSP frameworks, which is the basis for further applications. The elemental computation in DSP Frameworks is convolution. Convolution and LTI frameworks are the heart and soul of DSP. In this paper, the objective is to evaluate the performance of linear aand circular convolution using existing modified booth multiplication, also proposed a conversion of linear to circular conversion. The behavior of Linear Time Invariant (LTI) frameworks in nonstop time is depicted by Convolution indispensably while the behavior in discrete-time is depicted by Straight convolution. The results are evaluated using Verilog HDL is executed to confirm the performance parameters. The outcomes acquired utilizing Xilinx Simulation and Synthesis uncovers the usefulness of modified booth multiplications in developing the convolution tehniques.

Research Paper

Radar Pulse Compression Waveform Generation using FPGA Implementation

V. Narendra Reddy* , V. Lavanya **, B. Kiranmai***
*-** Department of Electronics and Communication, Maharaj Vijayaram Gajapathi Raj College of Engineering (Autonomous), Vizianagaram, Andhra Pradesh, India.
*** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology (Autonomous), Vizianagaram, Andhra Pradesh, India.
Reddy, V. N., Lavanya, V., and Kiranmai, B. (2019). Radar Pulse Compression Waveform Generation using FPGA Implementation. i-manager’s Journal on Digital Signal Processing. 7(2), 40-43. https://doi.org/10.26634/jdp.7.2.16790

Abstract

Pulse Compression (PC) techniques are utilized to obtain long range detection and better range resolution abilities in radar systems. Its implementation requires optimized and dedicated hardware. The real time implementation of this hardware have several constraints such as area occupied, power consumption, etc. This paper focus on designing an optimized structure, which can reduce area and power consumption. To provide flexibility in reconfiguration of this Linear Frequency Modulated (LFM) PC sequence has been generated on Field-Programmable Gate Array (FPGA) logic on Very Large Scale Integration (VLSI) architecture. It was found that the proposed structure has generated the LFM pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.