Secret Image Sharing Scheme Based on Compressed Sensing
Implementation of HOG Based Feature Extraction Method
Soldier Health and Position Monitoring System using GPS and IOT Technology
A Review on the Closed-Loop Strategy for Speed Control of BLDC Motors
V/F Based Speed Controller of Induction Motor using Ann Controller - A Review
Blockchain 3.0: Towards a Secure Ballotcoin Democracy through a Digitized Public Ledger in Developing Countries
Fetal ECG Extraction from Maternal ECG using MATLAB
Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities
Detection of Phase to Phase Faults and Identification of Faulty Phases in Series Capacitor Compensated Six Phase Transmission Line using the Norm of Wavelet Transform
A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR
A novel mathematical ECG signal analysis approach for features extraction using LabVIEW
Filtering of ECG Signal Using Adaptive and Non Adaptive Filters
Application of Polynomial Approximation Techniques for Smoothing ECG Signals
A Novel Approach to Improve the Wind Profiler Doppler Spectra Using Wavelets
Implementation of HOG Based Feature Extraction Method
In this work, a computational platform has been provided for a specific case study of infant cry analysis for identifying the abnormal infant cry, which is based on the principle of supervised classification, requiring the design of a proper knowledge base with a prior known normal infant cry samples called control sample. This research has a much focused 2-class problem, to be very precise it is a class and a complimentary class problem, where class refers to a healthy normal infant cry class and a complimentary-class refers to an unhealthy abnormal infant cry class. In this study, the authors have made use of Discrete Wavelet Transform (DWT), Mel Frequency Cepstral Coefficients (MFCC), Vector Quantization (VQ), and Euclidean Distance measure. The nearest match of the test infant cry sample is identified by correlating it with the infant cry samples present in the database and then it is classified as normal or abnormal (pathological) infant cry. The proposed method used 100 normal and 100 abnormal samples for training. The algorithm has been tested on the test dataset consisting of 25 normal and abnormal samples and the efficiency is found to be 96%.
Video watermarking is well known as the process of embedding copyright information in video bit streams. It has been proposed in recent years to solve the problem of illegal manipulation and distribution of digital video. In this study, the algorithm is based on cascade of two powerful mathematical transforms; Dual Tree Complex Wavelet Transform (DTCWT) and Singular Value Decomposition (SVD). RGB frames of the video is converted into YCbCr frames. For embedding, Y channel (luminance) is selected, then two dimensional Dual Tree Complex Wavelet Transform (DT-CWT) is applied on and then Singular Value Decomposition is applied on it. The same is performed on the watermark to be added. Then by convolving the host image and watermark image, watermarked signal is produced. Different quality metrics are also used, in order to determine the efficiency of the system retaining the watermark.
This paper demonstrates the experimental setup to acquire the stator current of single phase induction motor; and applies FFT technique to detect the fault in motor. The faults created in motor are bearing and rotor fault. Using current sensor, the signal under healthy state and faulty state is acquired from the motor, then using MATLAB signal processing toolbox the spectrum of the corresponding signal is obtained. The spectrum of the signal under fault is compared with the spectrum of the healthy signal and it is expected that the fault will be detected. The spectrum of the motor under healthy state is called the signature of the machine. This is unique for each machine. The central idea is that the signature of any machine under healthy and fault condition will be different. And, this forms the basis of condition monitoring and fault detection.
In this paper, the authors propose a fully reused high performance architecture to meet the needs of Radio communication which plays a vital role in the Wireless Sensor Nodes. These architectures utilize low power for their operation. In existing architecture the sensor nodes are limited potential to put the tradeoff between processing elements and design. The existing architecture has limited Processing Elements (PEs) that consumes less power and this existing architecture is used for off-the-shell low power microcontrollers which are not preferred for WSN. Most of the Wireless Sensor Network applications require the data to be processed at on-the-node processing. On-the-node processors consumes more power which is major limitation in VLSI. To overcome this limitation and extend the applications of their work, they have used suitable processing elements by taking the advantage of Folded-tree architecture which uses Parallel-prefix operations and thus power consumption is greatly minimized. The design is developed by using the Advanced Simulation and Synthesis tool Xilinx14.3 Design suite and Virtex6 FPGA for hardware Prototyping Environment. The design summary and synthesis report show that the proposed architecture consumes low power and works with high performance.
In this paper the power consumption is greatly is minimized by using efficient fault Tolerant Techniques. In a VLSI architecture one has to integrate millions of circuits on printed circuit board, at the same time the designer faces difficulty to deal with the Faulty ICs incorporated in the design. The faulty chips found in the circuit that needs to be replaced earlier may lead to the damage of the circuit entirely. For this the effective fault tolerant techniques are proposed. Some of them are Design for testability, Built in Self Test, Formal verification, and Functional Verification. The VLSI is a trade-off between Design Engineer and Test Engineer. Design Engineer focuses on efficient integration of millions of transistors on a PCB whereas the role of test engineer is to find fault in the circuit. In existing architecture independent programmable truncated multipliers are used to verify fault circuits and to achieve low power consumption benefits at the output Signal to Noise Ratio. But the method suffers with delay degradation factor. In this brief, the authors use programmable Truncated multiplier within the Digital Signal Processing architecture. With this the supply voltage is minimized. This fault technique improves the performance of fault designs, and reduces error correction burden. The Simulation and Synthesis results are verified on Xilinx14.3 design suite tool with Virtex6 FPGA prototyping Hardware Environment. The design summary results show that the proposed architecture consumes less power when compared to the previous architectures.
