VLSI Modeling of High Performance Digital Signal Processors for Wireless Sensor Nodes

P. Lokesh*, S. Chandana**, U. Somalatha***
*-*** Assistant Professor, VEMU Institute of Technology, Chittoor, Andhra Pradesh, India.
Periodicity:April - June'2017
DOI : https://doi.org/10.26634/jdp.5.2.13737


In this paper, the authors propose a fully reused high performance architecture to meet the needs of Radio communication which plays a vital role in the Wireless Sensor Nodes. These architectures utilize low power for their operation. In existing architecture the sensor nodes are limited potential to put the tradeoff between processing elements and design. The existing architecture has limited Processing Elements (PEs) that consumes less power and this existing architecture is used for off-the-shell low power microcontrollers which are not preferred for WSN. Most of the Wireless Sensor Network applications require the data to be processed at on-the-node processing. On-the-node processors consumes more power which is major limitation in VLSI. To overcome this limitation and extend the applications of their work, they have used suitable processing elements by taking the advantage of Folded-tree architecture which uses Parallel-prefix operations and thus power consumption is greatly minimized. The design is developed by using the Advanced Simulation and Synthesis tool Xilinx14.3 Design suite and Virtex6 FPGA for hardware Prototyping Environment. The design summary and synthesis report show that the proposed architecture consumes low power and works with high performance.


Digital Processor, Parallel Prefix Adder, Wireless Sensor Network (WSN).

How to Cite this Article?

Lokesh.P.,Chandana.S.,& Somalatha.U. (2017). VLSI Modeling of High Performance Digital Signal Processors for Wireless Sensor Nodes. i-manager’s Journal on Digital Signal Processing, 5(2), 22-30. https://doi.org/10.26634/jdp.5.2.13737


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