i-manager Publications

i-manager's Journal on Embedded Systems (JES)

Current Issue Vol. 12 Issue 2

Most Cited

Volume 2 Issue 1 February - April 2013

Research Paper

Design of High speed Modified Booth Encoded Parallel Multiplier

C. Padma* , Yarraballi Mahesh**

* M. Tech Student, Department of Electronics and Communication Engineering, CREC, Tirupathi, India.

** Assistant Professor, Department of Electronics and Communication Engineering, CREC, Tirupathi, India.

Padma.C., and Mahesh.Y. (2013). Design of High Speed Modified Booth Encoded Parallel Multiplier Using Carry Look Ahead Adder. i-manager’s Journal on Embedded Systems, 2(1), 1-6. https://doi.org/10.26634/jes.2.1.2238

Abstract

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding multiplier. Thus, the requirement of the modern computer system is a dedicated and very high speed multiplier unit that can perform multiplication operation on signed as well as unsigned numbers. The conventional Modified Booth Encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product. The Carry Save Adder (CSA) tree and the final Carry Look Ahead (CLA) adder used to speed up the multiplier operation. The resultant multiplier shows best performance than others. Since the proposed multiplier operates at GHz ranges.

References

[1]. W. –C. Yeh and C. –W. Jen, (2000). “High Speed Booth encoded Parallel Multiplier Design,” IEEE Transactions on Computers, (Vol. 49, No. 7, pp. 692-701, July).

[2]. Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, (2009). “Modified Booth multipliers with a Regular Partial Product Array,” IEEE Transactions on Circuits and systems-II, (Vol. 56, No. 5, May).

[3]. Li-Rong Wang, Shyh-Jye Jou and Chung-Len Lee,(2008). “A well-structured Modified Booth Multiplier Design”, (978-1-4244-1617-2/08/$25.00 ©IEEE).

[4]. Soojin Kim and Kyeongsoon Cho, (2010). “Design of High-speed Modified Booth Multipliers Operating at GHz Ranges,” World Academy of Science, Engineering and Technology, 61.

[5]. Magnus Sjalander and Per Larson-Edefors,(2008). “The Case for HPM-Based Baugh-Wooley Multipliers,” Chalmers University of Technology, Sweden, (March).

[6]. Z Haung and M D Ercegovac, (2005). “High performance Low Power left to right array multiplier design” IEEE trans.Computer, (Vol. 54, No.3, page 272-283, Mar).

[7]. Hsing-Chung Liang and Pao-Hsin Huang, (2007). “Testing Transition Delay Faults in Modified Booth Multipliers by Using C-testable and SIC Patterns” IEEE, (1-4244-1272-2/07).

[8]. Aswathy Sudhakar, and D. Gokila, (2010). “Run-Time Reconfigurable Pipelined Modified Baugh-Wooley Multipliers,” Advances in Computational Sciences and Technology ISSN 0973-6107 (Vol. 3, No. 2, pp. 223–235).

[9]. Myoung-Cheol Shin, Se-Hyeon Kang, and In-Cheol Park, (2010). “An Area- Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking,” Industry, and Energy through the project System IC, and by IC Design Education Center (IDEC).

[10]. Leandro Z. Pieper, Eduardo A. C. da Costa, Sérgio J. M. de Almeida,(2010). “Efficient Dedicated Multiplication Blocks for2´s Complement Radix- 2m Array Multipliers,” Journal of Computers, (Vol. 5, No. 10, October).

[11]. Pucknell Douglas A, Eshraghan, Kamran, (2003). “Basic VLSI Design,”Third edition, PHI Publication, (pp.242-243).

[12]. J. Fadavi-Ardekani, (1993). “M×N Booth Encoded Multiplier Generator Using Optimized Wallace Trees,” IEEE Trans. VLSI Systems, (Vol. 1, No. 2, June).

[13]. A.A.Farooquietal., (1998). ”General Data-Path Organization of a MAC Unit for VLSI Implementation of DSP Processors,” Proc. IEEE Int'l Symp. Circuits and Systems, (Vol. 2, pp. 260-263).

Full Article (HTML)

Pdf

Research Paper

A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique

S. Tabasum* , M.P. Chennaiah**

* M.Tech Student , SSITS, Rayachoty, Kadapa Dist., India.

** Associate Professor, SSITS, Rayachoty, Kadapa Dist., India.

Tabasum.S., and Chennaiah.M.P. (2013). A Parallel Multiplier - Accumulator Based on Radix - 2 Modified Booth Algorithm by Using Spurious Power Suppression Technique. i-manager’s Journal on Embedded Systems, 2(1), 7-13. https://doi.org/10.26634/jes.2.1.2239

Abstract

In this paper, the authors proposed a new architecture of Multiplier-And-Accumulator (MAC) for high-speed arithmetic. This can be implement by using radix-2 booth encoder .By combining multiplication with accumulation and devising a hybrid type of Carry Save Adder (CSA), the performance was improved. This includes the design exploration and applications of a Spurious-Power Suppression Technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs. Power dissipation is recognized as a critical parameter in modern VLSI field. In Very Large Scale Integration(VLSI), Low power VLSI design is necessary to meet MOORE'S law and to produce consumer electronics with more back up and less processing systems. The proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of power dissipation.

References

[1]. O.L. MacSorley, (1961). "High speed arithmetic in binary computers," Proc. IRE, Vol. 49, pp. 67-91, Jan. 1961.

[2]. A.D. Booth, (1952). "A signed binary multiplication technique," Quart. J. Math., Vol. 4, pp. 236-240, 1952.

[3]. C.S. Wallace, (1964). "A suggestion for a fast multiplier," IEEE Trans. Electron Comput., Vol. EC-13, No. 1, pp. 14-17, Feb. 1964.

[4]. A.R. Cooper, (1988). "Parallel architecture modified Booth multiplier," Proc. Inst. Electr. Eng. G, Vol. 135, pp. 125- 128, 1988.

[5]. N.R. Shanbag and P. Juneja, (1988). "Parallel implementation of a 4?4-bit multiplier using modified Booth's algorithm," IEEE J. Solid-State Circuits, Vol. 23, No. 4, pp. 1010-1013, Aug. 1988.

[6]. G. Goto, T. Sato, M. Nakajima, and T. Sukemura, (1992). "A 54?54 regular structured tree multiplier," IEEE J. Solid- State Circuits, Vol. 27, No. 9, pp. 1229-1236, Sep. 1992.

[7]. J. Fadavi-Ardekani, (1993). "MN Booth encoded multiplier generator using optimized Wallace trees," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 1, No. 2, pp. 120-125, Jun. 1993.

[8]. N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka,A. Shimizu,K. Sasaki,and Y. Nakagome, (1995). "A 4.4 ns CMOS 54?54 multiplier using pass-transistor multiplexer”, IEEE J. Solid-State Circuits, Vol. 30, No. 3, pp. 251-257, Mar. 1995.

[9]. A. Tawfik, F. Elguibaly, and P. Agathoklis, (1997). "New realization and implementation of fixed-point IIR digital filters," J. Circuits, Syst., Comput., Vol. 7, No. 3, pp. 191- 209, 1997.

Full Article (HTML)

Pdf

Research Paper

Clock Pair Shared Pulsed Flipflop

P. Hemanth Kumar* , G. Rajesh**

* M.Tech Student, CREC, Tirupati, India.

** Associate Professor, ECE, CREC, Tirupati, India.

Kumar,H.P., and Rajesh.G. (2013). Clock Pair Shared Pulsed Flipflop. i-manager's journal on Embedded Systems, 2(1), 14-16. https://doi.org/10.26634/jes.2.1.2235

Abstract

Low power flip-flops which play a vital role for the design of low-power digital systems. Flip flops and latches consume large amount of power due to redundant transitions and clocking system. In addition, the energy consumed by low skew clock distribution network is steadily increasing and becoming a larger fraction of the chip power. Almost, 30% -60% of total power dissipation in a system is due to flip flops and clock distribution network. In order to achieve a design that is both high performances while also being power efficient, careful attention must be paid to the design of flip flops and latches. The authors survey a set of flip flops designed for low power and High performance.

References

[1]. Gronowski, P.E, W.J. Bowhill, R.P. Preston, R.K. Gowanand R.L. Allmon, (1998). High-performance microprocessor design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 33, No. 5, pp. 676–686, May. 1998.

[2]. Partovi .H, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper. (1996). Flow-through latch and edge triggered flip-flop hybrid elements, in ISSCC Dig., Feb.1996, pp. 138– 139.

[3]. Klass .F, C. Amir, A. Das, K. Aingaran, C. Truong,R.Wang, A.Mehta, R. Heald, and G. Yee. (1998). Semi dynamic and dynamic flip-flops with embedded logic, in Symp. VLSI Circuits, Dig. Tech. Papers, pp.108–109, June 1998.

[4]. Kim C. L. and S. Kang. (2002). A low-swing clock double edge-triggered flip-flop, IEEE J.Solid-State Circuits, Vol.37, N no. 5, pp. 648–652, May 2002.

[5]. J.C. Park, V. J. Mooney III and P. Pfeiffenberger. (2004). Sleepy Stack Reduction of Leakage Power, Proceeding of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158, September 2004.

Full Article (HTML)

Pdf

Research Paper

Fault Analysis on Grid Connected MPPT BasedPhotovoltaic System

Sibasish Panda* , Anup Kumar Panda, H.N Pratihari*

* Assistant Professor, Department of Electrical and Electronics Engineering, Centurion University of Technology & Management, India.

Professor & Head, Department of Electrical Engineering, NIT Rourkela, Rourkela, Odisha, India.

* Professor, Department of Electronics & Communication Engineering, Centurion University of Technology & Management, India.

Panda,S., Panda,A,K., and Pratihari.H.N. (2013). Fault Analysis on Grid Connected MPPT Based Photovoltaic System. i-manager’s Journal on Embedded Systems, 2(1), 17-28. https://doi.org/10.26634/jes.2.1.2236

Abstract

This paper presents the simulation model of a 3.5 kW PV array followed by a boost converter, which boost up the output voltage of the PV array. Maximum Power Point Tracking (MPPT) can effectively improve the solar energy conversion efficiency of PV array, in this paper Perturb- and – Observe (P&O) algorithm has been used to achieve this function. Grid connected PV system needs a three phase inverter for synchronization. The inverter control system modeling has been carried out in Matlab/Simulink 2010 environment with the aids of the proportional-integral controllers, sinusoidal vectored pulse width modulation technique and park transformation. Phase Locked Loop (PLL) is used to lock the grid frequency and phase. Finally different types of AC faults are created on the grid side and Total Harmonic Distortion (THD) is calculated in each of the case.

References

[1]. J.P. Benner and L. Kazmerski, (1999) “Photovoltaics gaining greater visibility,” IEEE Spectr., Vol. 36, No. 9, pp. 34–42, Sep. 1999.

[2]. Stember LH. (1981). “Reliability considerations in the design of solar photovoltaic power systems.” Solar Cells 1981;3(3):269-285.

[3]. Hamdy MA, Beshir ME, Elmasry SE. “Reliability analysis of photovoltaics systems.” Applied Energy 1989;33(4):253-263.

[4]. David M. Bressoud. Radical Approach to Real Analysis, 2nd edition, 2006.

[5]. Marcelo Gradella Villalva, Jonas Rafael Gazoli, Ernesto Ruppert Filho. Modeling and Circuit-based Simulation of Photovoltaic Arrays, University of Campinas (UNICAMP), Brazil.

[6]. D. Sera, R. Teodorescu, and P. Rodriguez. (2007). “PV panel model based on datasheet values.” In Proc. IEEE International Symposium on Industrial Electronics, ISIE, p. 2392–2396, 2007.

[7]. W. De Soto, S.A. Klein, and W.A. Beckman. (2006). Improvement and validation of a model for photovoltaic array performance. Solar Energy, 80(1):78–88, January 2006.

[8]. A. Driesse, S. Harrison, and P. Jain. (2007). “Evaluating the effectiveness of maximum power point tracking methods in photovoltaic power systems using array performance models.” In Proc. IEEE Power Electronics Specialists Conference, PESC, p. 145–151, 2007

[9]. Q. Kou, S.A. Klein, and W.A. Beckman. (1998). “A method for estimating the long-term performance of direct-coupled PV pumping systems,” Solar Energy, 64(1-3):33–40, September 1998.

[10]. R.A. Messenger and J. Ventre. (2004). Photovoltaic Systems Engineering. CRC Press, 2004.

[11]. K.H. Hussein, I. Muta, T. Hoshino, and M. Osakada. (1995). “Maximum photovoltaic power tracking: an algorithm for rapidly changing atmospheric conditions.” In Generation, Transmission and Distribution, IEE Proceedings-, v. 142, p. 59–64, January 1995.

[12]. Milan Pradanovic & Timothy (2003). Green, ?Control and filter design of three phase inverter for high power quality grid connection, ? IEEE Transactions on Power Electronics, Vol.18. pp.1- 8, January 2003.

[13]. C Y Wang, Zhinhong Ye& G. Sinha, (2003). ? Output filter design for a grid connected three phase inverter,?Power electronics Specialist Conference, pp.779-784, PESE 2003.

[14]. Samul Araujo& Fernando Luiz, (2007). ? LCL fiter design for grid connected NPC inveters in offshore wind turbines ll7th International conference on Power Electronics, pp. 1133-1138, October 2007.

[15]. S.K. Chung, (2000). “Phase lock loop for grid connected 3 phase power conversion system,” ? IEE Proc. Electr. Power Application, Vol. 147, pp. 213 - 219, May 2000.

[16]. Guan Chyan Hsieh & James .C Hung, (1999). “Phase- Lock Loop Techniques - A Survey,” // IEEE Transaction on Industrial Electronics, Vol. 43, pp. 50- 60, December1999.

[17]. Xiao-Qiang GUO, Wei-Yang WU, He-Rong GU, (2011). “Phase locked loop and synchronization methods for grid-interfaced converters: a review”, PRZEGLAD ELEKTROTECHNICZNY (Electrical Review), 2011.

[18]. P. Tripura, Y.S. Kishore Babu, Y.R. Tagore, (2011). “Space Vector Pulse Width Modulation Schemes for Two-Level Voltage Source Inverter”, ACEEE Int. J. on Control System and Instrumentation Vol. 02, No. 03, October 2011.

Full Article (HTML)

Pdf

Research Paper

Microcontroller based Under/Over Voltage and Double Phasing Fault ProtectionSystem: Design and Simulation

M. Rizwan Khan* , Basharat Ahmad**

*-** Assistant Professor, Department of Electrical Engineering, Zakir Hussain College of Engineering & Technology, Aligarh Muslim University, Aligarh, U.P. India.

Khan,R.M., and Ahmad,B. (2013).Microcontroller Based Under/over Voltage and Double Phasing Fault Protection System: Design and Simulation. i-manager’s Journal on Embedded Systems, 2(1), 29-35. https://doi.org/10.26634/jes.2.1.2237

Abstract

A microcontroller based system is designed and developed to protect the house hold electrical appliances, from double phasing fault and fluctuation of line voltages. This device is tested with upper and lower cutoff voltages set at 150V rms as lower Limit and 250V rms as Upper Limit for the desired voltage range. The system is simulated and tested on Matlab R2010b and then implemented. The ATMega16 Microcontroller from ATMEL is used to implement the system. The Hex file for the microcontroller is developed using Code Vision CVAVR Programming pad and compiler.

References

[1]. P.D. Abramo, R. Roncella, R. Saletti, (2001). “Power-Supply Over Voltage Protection Circuit for Motor Cycle ON-board Electronics,” Southwest Symposium on Mixed-Signal Design, (SSMSD, pp.162-166).

[2]. M. Abdullah-Al-Mashud, M.A.A. Tariq, M. Shamim Hossain, Md. Serajul Islam, (2012). “Design and Development of a low cost microcontroller based single phase water pump controller” International Journal of Information sciences and Techniques.(IJIST), Vol. 2, No. 4, pp. 49-56.

[3]. R.N. Buono, (1998). “Shunt regulator provides over voltage protection”, EDN Magazine, (pp. 103-104 January).

[4]. F. Pulvirenti, P. Milazzo, R. Ursino, “Charger Power Switch for mobile phones”, Proc. of 2nd IEEECAS Region 8 Workshop on Analog and Mixed IC Design.

[5]. K. Sakamoto, Y. Nunogawa, K. Satonaka, T. Kouda, S. Horiuchi, “An intelligent power IC with reverse battery protection for fast-switching high-side solenoid drive”, IEEE Trans. on Electron Devices, (Vol. 46, N. 8, August).

[6]. R.J. Valentine, (1996). “Protection techniques ensure IC reliability in power-control circuits”, EDN Magazine, October.

[7]. M.A. Mazidi, R.M. Kinlay and D. Causey, (2008). “PIC Microcontroller”, Prentice Hall Inc.

[8]. J.B. Peatman, (1997). “Design with PIC microcontroller”, Prentice Hall Inc.

i-manager's Journal on Embedded Systems (JES)

Current Issue Vol. 12 Issue 2

Most Read

Most Cited

Volume 2 Issue 1 February - April 2013

Design of High speed Modified Booth Encoded Parallel Multiplier

C. Padma* , Yarraballi Mahesh**

* M. Tech Student, Department of Electronics and Communication Engineering, CREC, Tirupathi, India. ** Assistant Professor, Department of Electronics and Communication Engineering, CREC, Tirupathi, India.

Padma.C., and Mahesh.Y. (2013). Design of High Speed Modified Booth Encoded Parallel Multiplier Using Carry Look Ahead Adder. i-manager’s Journal on Embedded Systems, 2(1), 1-6. https://doi.org/10.26634/jes.2.1.2238

Abstract

References

Full Article (HTML)

Pdf

A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique

S. Tabasum* , M.P. Chennaiah**

* M.Tech Student , SSITS, Rayachoty, Kadapa Dist., India. ** Associate Professor, SSITS, Rayachoty, Kadapa Dist., India.

Tabasum.S., and Chennaiah.M.P. (2013). A Parallel Multiplier - Accumulator Based on Radix - 2 Modified Booth Algorithm by Using Spurious Power Suppression Technique. i-manager’s Journal on Embedded Systems, 2(1), 7-13. https://doi.org/10.26634/jes.2.1.2239

Abstract

References

Full Article (HTML)

Pdf

Clock Pair Shared Pulsed Flipflop

P. Hemanth Kumar* , G. Rajesh**

* M.Tech Student, CREC, Tirupati, India. ** Associate Professor, ECE, CREC, Tirupati, India.

Kumar,H.P., and Rajesh.G. (2013). Clock Pair Shared Pulsed Flipflop. i-manager's journal on Embedded Systems, 2(1), 14-16. https://doi.org/10.26634/jes.2.1.2235

Abstract

References

Full Article (HTML)

Pdf

Fault Analysis on Grid Connected MPPT BasedPhotovoltaic System

Sibasish Panda* , Anup Kumar Panda**, H.N Pratihari***

Panda,S., Panda,A,K., and Pratihari.H.N. (2013). Fault Analysis on Grid Connected MPPT Based Photovoltaic System. i-manager’s Journal on Embedded Systems, 2(1), 17-28. https://doi.org/10.26634/jes.2.1.2236

Abstract

References

Full Article (HTML)

Pdf

Microcontroller based Under/Over Voltage and Double Phasing Fault ProtectionSystem: Design and Simulation

M. Rizwan Khan* , Basharat Ahmad**

*-** Assistant Professor, Department of Electrical Engineering, Zakir Hussain College of Engineering & Technology, Aligarh Muslim University, Aligarh, U.P. India.

Khan,R.M., and Ahmad,B. (2013).Microcontroller Based Under/over Voltage and Double Phasing Fault Protection System: Design and Simulation. i-manager’s Journal on Embedded Systems, 2(1), 29-35. https://doi.org/10.26634/jes.2.1.2237

Abstract

References

Full Article (HTML)

Pdf

* M. Tech Student, Department of Electronics and Communication Engineering, CREC, Tirupathi, India.

** Assistant Professor, Department of Electronics and Communication Engineering, CREC, Tirupathi, India.

* M.Tech Student , SSITS, Rayachoty, Kadapa Dist., India.

** Associate Professor, SSITS, Rayachoty, Kadapa Dist., India.

* M.Tech Student, CREC, Tirupati, India.

** Associate Professor, ECE, CREC, Tirupati, India.

Sibasish Panda* , Anup Kumar Panda, H.N Pratihari*