Clock Pair Shared Pulsed Flipflop

P. Hemanth Kumar*, G. Rajesh**
* M.Tech Student, CREC, Tirupati, India.
** Associate Professor, ECE, CREC, Tirupati, India.
Periodicity:February - April'2013
DOI : https://doi.org/10.26634/jes.2.1.2235

Abstract

Low power flip-flops which play a vital role for the design of low-power digital systems. Flip flops and latches consume large amount of power due to redundant transitions and clocking system. In addition, the energy consumed by low skew clock distribution network is steadily increasing and becoming a larger fraction of the chip power. Almost, 30% -60% of total power dissipation in a system is due to flip flops and clock distribution network. In order to achieve a design that is both high performances while also being power efficient, careful attention must be paid to the design of flip flops and latches. The authors survey a set of flip flops designed for low power and High performance.

Keywords

Flip Flop, Low Power, CMOS Circuit.

How to Cite this Article?

Kumar,H.P., and Rajesh.G. (2013). Clock Pair Shared Pulsed Flipflop. i-manager's journal on Embedded Systems, 2(1), 14-16. https://doi.org/10.26634/jes.2.1.2235

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