Hardware Implementation of Artificial Neural Networks

K.V. Ramanaiah*, Siripurapu Sridhar**
* YSR Engineering College, Yogi Vemana University, India.
** LENDI Institute of Engineering and Technology, India
Periodicity:November - January'2015
DOI : https://doi.org/10.26634/jes.3.4.3514


Soft computing Artificial Neural Networks (ANN) represent a family of statistical learning models inspired by the biological nervous systems for approximating functions based on large number of unknown inputs. Artificial Neural Networks are comprised of simple processing Neuron elements that possess numeric weighted interconnections arranged in a layered fashion, which can be tuned to make them adaptive to the given inputs. Hardware architectures for implementation of soft computing multi layer perceptron type feed forward artificial neural networks (MLPFFNN) targeting Field Programmable Gate Arrays (FPGA) are presented. Hardware realization of ANN, to a large extent depends on the efficient implementation of a single neuron. Parallel digital system MLPFFNN architecture is designed in Verilog HDL language. The fast processing tendency of parallel neural network architectures makes them more suitable for implementation in VLSI technology. FPGA realization of ANNs with a large number of neurons is still a challenging task. The proposed neural network architecture is implemented in two phases; First phase includes training the neural network using MATLAB program, the second phase of implementation included the hardware implementation of trained parallel neural network targeting Xilinx high performance Virtex family FPGA devices. Hardware realization of ANNs with a large number of neurons is still a challenging task.


Neural Networks, Backpropagation, Compression, Decompression, VLSI, FPGA

How to Cite this Article?

Ramanaiah.K.V., and Sridhar,S. (2015). Hardware Implementation of Artificial Neural Networks. i-manager’s Journal on Embedded Systems, 3(4), 31-34. https://doi.org/10.26634/jes.3.4.3514


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