Design and Implementation of Robot Assisted Arduino Based Object Recognition and Sorting
Wireless Charging System for Electric Vehicle
Embedded System-Based Enhanced Smart Security Systems for Intelligent Monitoring Applications: A Review
Arduino-Based Vehicle Collision Detection and Warning System
WiFireBot: Smart ESP32 Based Surveillance Car with Temperature and Fire Detection
Verilog Based UART System Design
IoT based Smart Agriculture Monitoring Framework with Automation
Intel ® Processor Architectural and Integrated Development Environment Exploration
An Integrated Model of Digital Fuel Indicator and GPS Tracking System for Vehicles
Designing of an Embedded system for Wireless Sensor Network for Hazardous Gas leakage control for industrial Application
Hardware Implementation of Artificial Neural Networks
Fault Analysis on Grid Connected MPPT BasedPhotovoltaic System
High Efficiency Hybrid Intelligent Street Lighting Using A Zigbee Network And Sensors
Design of Dual-Band Bandpass Filter Using Interdigital Embedded Open Loop Triangular Resonator Loaded with Stubs
License Plate Localization Using Novel Recursive Algorithm And Pixel Count Method
In recent times self-repairing digital systems have emerged as the most favorable alternative for fault-tolerant systems. However, such systems are still unrealistic in many cases, predominantly due to the complex rerouting process that follows cell replacement. They lose efficiency when the circuit size surges, due to extra hardware besides the functional circuit and the non-utilization of normal operating hardware for fault recovery. In Endocrine cellular communication, when an endocrine cell dies in a specific process, the collection of cells and tissues of an organism secretes a hormone and its connections are maintained through blood vessels. Inspired by this communication process, a system has been proposed which reduces hardware overhead to maintain good fault coverage. A fault recovering system is proposed by the use of genetic algorithm to increase the lifetime of the digital circuits. Genetic Algorithms are often expected to design combinational circuits with the fault-tolerant and self-repair ability, Spare cells are used as a replacement in case of failures occurring in working cells. Comparing with the existing methods, the mechanism proposed will be efficient for the real fault tolerant systems.
The usage of vehicles have been increased in large urban areas causing heavy traffic in signals. It is one of the main reasons for miserable accidents in urban areas. In conventional traffic control system, there is a situation where GREEN signal is ON when high number of vehicles are present in the particular lane. If RED signal is ON, then it shows that low number of vehicles are present in that lane. When there is no vehicle in that lane means, YELLOW signal is ON. The smart traffic control system employs dynamic time management algorithm which avoids such contradictions. According to this system, contradiction can be eliminated using an IR Sensor and MSP430 Microcontroller. If there are high numbers of vehicles in that lane, it can be detected using the IR Sensor. The MSP430 Microcontroller is programmed accordingly, switches the traffic light facilitating the flow of number of vehicles in particular lane. If the number of vehicles is high in a lane, then the Microcontroller maintains the vehicle movement in low number lane until the pre-set time runs out. So the uniform traffic flow is maintained. The system gives the first priority to high flow lane. This paper is used for controlling traffic signals, air pollution and reduces the man power.
A real-time operating system (RTOS) is a piece of code (usually called the kernel) that controls task allocation when the microcontroller is operating in a multi-tasking environment. RTOS (Real time operating system) selected OSA (Open system Architecture) OS (Operating System) for the project. In the project, the authors were controlling the industrial equipment with the help of the microcontroller. In this, the major parts of industries were to be maintained. The controls maintained are temperature management, entering into restricted area of the industry, emergency alarm and displaying such parameters. In processing, there are some ways of algorithm and processes which were followed by the OS. The processes are 1) Context switching - while running a task switching to another task. 2) Multitasking - running more number of tasks at a time. 3) Interrupt handling – is the process of task with high priority which will execute first by passing the running task. The algorithm followed is priority based system where in the task were executing in priority bases and the priority was given by the authors in the coding part. The tasks have the same priority that follow the round robin algorithm, which shares the running time by separating equal time slots. For example, two tasks of same priority will run for 5ms and switch to other task that runs for 5ms and switched again. These were the processes and algorithms that were followed in the OS. In the project, temperature is maintained for certain level by temperature sensor (LM35), if it reaches above the level, the fan is switched on. When PIR sensor sense live human, it will switch on the light. For emergency case, alarm would on by pressing the emergency button, different temperatures is were maintained by different sensors and are processed to the output with the help of the OSA RTOS.
A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The direct current sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses Newton Raphson method to obtain switching angles offline for different dc source values. Then, fuzzy logic controllers are used to determine the switching angles that correspond to the real time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at anytime, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results.
The quantum cellular automata is the basis for computing Nanotechnology based designs. The QCA cells are based on cells of coupled quantum dots that are featured at nanometer scale. As multipliers are the major computing elements in any arithmetic unit, several designs have emerged to improve performance, decrease area and consume less power. The tree based structures prove better designs of multipliers when compared to conventional designs. In this paper, a 4x4 Wallace tree multiplier is developed using majority gate structures. The design is developed using Verilog HDL and are functionally verified using ISIM simulator. The synthesis is carried out in Xilinx ISE synthesizer and the results are proved to be optimized in terms of delay and area.
FPGA based E-Learning system is centered on the reduction of problems on the learning activities for better education in a global and information society. E-learning exploits interactive technologies and communication systems to improve the learning experience. It entirely transforms the way we teach and learn across the board. It will raise standards, and widen participation in lifelong learning. It is soon to become the dominant form of education in the world. A lot of effort is made for improving the work methods and communication among students and professors, to bettering the quality of this kind of studying. The traditional learning provides less interest and interactive classes between the faculties and the students. To overcome these restrictions, this type of visual based audio E-Learning system was created for primary school students. The software tools used were Eclipse-C or Xilinx. Unified Learning Kit (ULK) control panel is used as an output panel and it links the hardware system. Spartan 6 FPGA and TI OMAP Processor is the main functional module in the Hardware system.
