Verilog Based UART System Design
IoT based Smart Agriculture Monitoring Framework with Automation
Intel ® Processor Architectural and Integrated Development Environment Exploration
An Integrated Model of Digital Fuel Indicator and GPS Tracking System for Vehicles
Designing of an Embedded system for Wireless Sensor Network for Hazardous Gas leakage control for industrial Application
Hardware Implementation of Artificial Neural Networks
Fault Analysis on Grid Connected MPPT BasedPhotovoltaic System
High Efficiency Hybrid Intelligent Street Lighting Using A Zigbee Network And Sensors
License Plate Localization Using Novel Recursive Algorithm And Pixel Count Method
Design of Dual-Band Bandpass Filter Using Interdigital Embedded Open Loop Triangular Resonator Loaded with Stubs
Arithmetic error-control codes have been used to protect data transmission and processing. These codes are implemented through the use of appropriate encoding/decoding devices. An important part of these devices is a residue computing circuit, which has also found its application in mixed-signal systems testing. Arithmetic error-control codes originated to protect data transfers over binary channels; therefore the design methodology for residue computing circuits has been mostly oriented to the binary case. A non-binary design technique has only been known for the special type of compaction modulo. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. The compaction process causes some errors in the data being compacted to escape from detection. It is assumed that these data are distorted (the rate of distortion is known), which additionally increases the error escape rate. We show how to design compaction circuits that do not increase the error escape rate due to distortion.
A Threshold based fixed 3x3 filter for the removal of long tailed noise (impulse) and artifacts in images is proposed. The processing pixels are arranged in increasing order using a novel snake like sorting for finding median. The algorithm detects the corrupted pixel, if the absolute difference between the processed pixel and the unsymmetrical trimmed median is greater than a fixed threshold else termed as non noisy. Under high noise densities the computed median might also noisy. Hence the absolute difference of the median and unsymmetrical trimmed median filter is greater than second threshold then the corrupted pixels are replaced by the trimmed median of the current processing window else median is replaced else if condition fails the processed pixels is left unaltered. The filtering window is kept fixed at 3x3 for increasing noise densities. The proposed algorithm shows good results quantitatively and qualitatively when compared to existing and recent filters. The proposed algorithm is tested against different grayscale images and it gives higher Peak Signal-to-Noise Ratio (PSNR), low Mean square error (MSE) and good Image Enhancement Factor (IEF) with edge preservation capabilities even at very high noise densities. The proposed Algorithm is non adaptive and can replace several individual algorithms for the removal of different artifacts.
The most commonly method use by people to protect their secured data or information is using password or PIN/ID protection. This method require user to authenticate them by entering password that they had already created. However, due to lack of security the data is not secured enough. There are cases of fraud and theft when people can easily know the password. But as time goes by, there is a new technology known as Biometric Identification System. It uses biometric characteristics of an individual that is unique and different from everyone else and therefore can be use to authenticate the user authority access. This paper focused on an implementation of speech recognition as medium security access control to restricted services such as phone banking system, voicemail or access to database services. First, speaker signal will go to pre-treatment process, where it will remove the background noise. Then, features from speech signal will be extracted using Mel Frequency Cepstrum Coefficients (MFCC) method. Then, using Vector Quantization, the features will be matched with the reference speech in database. The real speaker is identified by clustering the speech signal from the tested speaker to codebook of each speaker using K-means algorithm and the speaker with the lowest distortion Euclidean distances is chose as the correct speaker. The main focus of this research is speaker identification, which compared speech signal from unknown speaker to a database of known speaker using text-dependent utterances. From the experimental results shows that the method developed is able to recognize the correct voice source perfectly.
This paper presents an FPGA based waveform generator for Micro-SAR (µSAR). µSAR is a low-cost, light-weight, and low power consumption (18 watts) for Unmanned Aerial Vehicle (UAV) based applications. A chirp signal offers the advantages of better range accuracy, range resolution and Doppler sensitivity. In addition, better signal to noise ratio (SNR) and higher bandwidth, as compared to other pulse compression techniques prompts us to choose Linear Frequency Modulation Continuous Wave (LFM-CW). In this paper different architectures of DDS have been discussed. In particular DDS based on Look Up Table (LUT), CORDIC algorithm and IIR filter have been implemented. Finally, a chirp signal required for µSAR is generated using LUT based DDS, based on parameters specified by Brigham Young University µSAR system.
IC Designers are struggling for tradeoff between significant variation effects and very tight power constraints in current nanometer regime. Usage of conventional timing safety margin approach becomes the cause of continuous power consumption to prevent the design from low probability timing variations. Various solutions have been proposed to achieve optimized power consumption/dissipation. Dynamic Threshold Voltage Vth Scaling (DVTS), Dynamic Voltage Scaling (DVS) and Dynamic Voltage and Frequency Scaling (DVFS) are some of the reported techniques in literature to achieve optimized power consumption. These approaches deals with aggressive standby Vth and VDD scaling by tracking PVT variations to smartly tradeoff between safety of data and decreased power consumption. In this paper different power saving strategies are discussed along with their benefits and limitations. This study will be helpful to select an effective power saving strategy to minimize the power dissipation.