Secret Image Sharing Scheme Based on Compressed Sensing
Implementation of HOG Based Feature Extraction Method
Soldier Health and Position Monitoring System using GPS and IOT Technology
A Review on the Closed-Loop Strategy for Speed Control of BLDC Motors
V/F Based Speed Controller of Induction Motor using Ann Controller - A Review
Blockchain 3.0: Towards a Secure Ballotcoin Democracy through a Digitized Public Ledger in Developing Countries
Fetal ECG Extraction from Maternal ECG using MATLAB
Brief Introduction to Modular Multilevel Converters and Relative Concepts and Functionalities
Detection of Phase to Phase Faults and Identification of Faulty Phases in Series Capacitor Compensated Six Phase Transmission Line using the Norm of Wavelet Transform
A Novel Approach to Reduce Deafness in Classical Earphones: MUEAR
A novel mathematical ECG signal analysis approach for features extraction using LabVIEW
Filtering of ECG Signal Using Adaptive and Non Adaptive Filters
Application of Polynomial Approximation Techniques for Smoothing ECG Signals
A Novel Approach to Improve the Wind Profiler Doppler Spectra Using Wavelets
Implementation of HOG Based Feature Extraction Method
In many institutions, during each examination, the only requirement that is needed for a student to enter ex- amination hall is his/her identity card, which is checked for authenticity and validity of the student. This process does fail to identify if such a student is eligible to write that examination. Currently with the high ratio of students to invigilators in many examination halls, using only ID card for verification does not show whether a student registered for a subject or not. As a result, some students make use of this loophole to request the assistance of another student from another level or other department to help them sit and write the exam on their behalf. This act is impersonation and thus, is an act of examination malpractice. In this paper, an examination eligibility verification system using quick response code was developed. The EEV system was designed using UML diagrams and implemented using JavaScript, Cascading Style Sheet, and HTML5 in Microsoft Visual Studio Code for the front-end, and PHP and MySQL relational database management system for the back-end. The EEV system was validated using smart- phone to scan the QR code generated. It was observed that the system took 4 seconds to verify a student’s eligibility status. This shows that 300 students can be verified in 20 minutes. Furthermore, it provides a log file that keeps track of eligible students, which serve the purpose of attendance. So, the EEV system was friendly, secure and reliable, and has fast response time.
The research work aimed at creating a smart campus map of Federal University of Technology, Bosso Campus, Minna, Niger State, Nigeria. The advancement of technology with an attendant emergence of digital maps is gradually phasing out obsolete paper maps. One of the problems inherent with paper maps is the difficulty visitors face in navigating the campus. The study utilized ArcGIS as the main digital mapping software. It was used for digitization and simulation of map features. Google Earth pro 7.1 was used to extract and download satellite image of Bosso campus, which was georeferenced to have the actual earth projection of the campus. The procedures employed include digitization, assignment of attributes to features, creation and editing of the map and finally, conversion of the map to KML format (the format that can be read by ArcGIS software), the utilization of Android Studio as an interactive software. The converted map is imported and overlaid with Google API 21. The Smart map is an interactive software between users and various objects in the visual environment, which further provides great convenience for the users to understand geographical environment and campus information of Bosso campus. The study demonstrates the potentials of digital mapping using GIS software and Android Studio in creating and managing spatial data. Smart digital map can be used as a tool to formulate development plans not only in the campus, but also for wider coverage areas.
Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial Neural Networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.
This paper presents railway track fault monitoring approach using signal processing techniques operator-based on signal separation. The measured vibration signal is first pre-processed using the Kalman filtering to filter the noise imposed on the signal. A specific band of frequency is identified using Finite Impulse Response (FIR) filter then an operator-based signal separation approach, called null space pursuit (NSP), is applied to decomposing the signal into a series of subcomponents and residues in accordance with their characteristics. Subsequently, the selected subcomponent with the maximum kurtosis value is analyzed by the envelop spectrum to identified potential fault-related characteristic frequency components. Experimental studies from the signals observed from railway track during the motion of the train have verified the effectiveness of the present approach for railway track fault monitoring system.
In this paper, the Merged Delay Transformation approach has been employed in order to design Infinite Impulse Response-Decimation Filter (IIR-DF) and it has also been proved that this approach is an efficient approach for designing IIR-DF. In the proposed approach called as; MDT-IIR-DF, filtering followed by Sampling Rate Compression (decimation process) is obtained in a single stage instead of two separate stages as in conventional IIR Filters which in turn reduces the cost of computation in terms of number of multipliers per output samples. Two Examples have been included which show that the cost of computation for proposed approach; MDT-IIR-DF is low as compared to the cost of computation for various conventional Filters like: Polyphase FIR, Conventional IIR and Polyphase IIR, respectively. The proposed approach; MDT-IIR-DF is better computationally efficient in which the computational efficiency is increased by merging the M number of delay elements in recursive part together so that the current output can be directly computed from Mth old output. Magnitude and Phase Response of various MDT based IIR filters like; Butterworth, Chebyshev-I, Chebyshev-II and Elliptical flters have been compared with conventional Butterworth, Chebyshev-I, Chebyshev-II and Elliptical IIR filters (without MDT approach). The simulation results show that same magnitude and phase response for both (with and without MDT approach) filters i.e. the MDT based IIR-DF has close agreement with conventional IIR filter at low computational cost along with afficient architecture.
