References
[1]. Alioto, M., Fort, A., Pancioni, L., Rocchi, S., Vignoli, V.,
Dipartimento, D. I. I., and Siena, U. (2005). “An Approach to
the Design of PFSCL Gates”. IEEE International Symposium
on Circuits and Systems, Vol. 2, pp. 2437–2440.
[2]. Alioto, M., and Palumbo, G. (2003). “Design Strategies
for Source Coupled Logic Gates”. IEEE Transactions on
Circuits and Systems I: Fundamental Theory and Applications,
Vol. 50, No. 5, pp. 640–654.
[3]. Allan, V.H., Jones, R.B., Lee, R.M., and Allan, S.J. (1995).
“Software Pipelining”. ACM Computing Surveys, Vol. 27, No.
3, pp. 367–432.
[4]. Allstot, D.J., San-Hwa Chee, S.H., Kiaei, S., and
Shrivastawa, M. (1993). “Folded Source-Coupled Logic vs.
CMOS Static Logic for Low-Noise Mixed-Signal ICs”. IEEE
Transactions on Circuits and Systems I: Fundamental
Theory and Applications, Vol. 40, No. 9, pp. 553–563.
[5]. Gupta, K., Pandey, N., and Gupta, M. (2012).
“Multithreshold MOS Current Mode Logic Based
Asynchronous Pipeline Circuits”. ISRN Electronics, Vol. 2012
(2012), pp. 7.
[6]. Gupta, K., Pandey, N., and Gupta, M. (2013). “MCML
D-Latch using Triple-Tail Cells: Analysis and Design”. Active and Passive Electronic Components, Vol. 2013 (2013), pp. 9.
[7]. Gupta, K., Sridhar, R., and Chaudhary, J. (2011).
“Performance Comparison of MCML and PFSCL Gates in
0.18 µm CMOS Technology”. 2 International Conference
on ICCCT, Vol. 1, No. 1, pp. 230–233.
[8]. Kang, S.M., and Leblebici, Y. (2003). CMOS Digital
Integrated Circuits : Analysis and Design. Tata McGraw-Hill.
[9]. Kimura, K. (1995). “Circuit Design Techniques for very
Low-voltage Analog Functional Blocks using Triple-tail Cells”.
IEEE Transactions on Circuits and Systems I: Fundamental
Theory and Applications, Vol. 42, No. 11, pp. 873–885.
[10]. Musa, O., and Shams, M. (2010). “An Efficient Delay
Model for MOS Current-Mode Logic Automated Design
and Optimization”. IEEE Transactions on Circuits and
Systems I: Regular Papers, Vol. 57, No. 8, pp. 2041–2052.
[11]. Nowick, S.M. (2011). “ High-Per formance
Asynchronous Pipelines : An Overview”. IEEE Design and Test
of Computers, pp. 8–22.
[12]. Pandey, N., Gupta, K., and Gupta, M. (2014). “An Efficient Triple-tail Cell based PFSCL D Latch”.
Microelectronics Journal, Vol. 45, No. 8, pp. 1001–1007.
[13]. Rabaey, J. M., Chandrakasan, A., and Nikolic, B.
(2003). Digital Integrated Circuits: A Design Perspective. 2
ed., Prentice Hall Electronics and VLSI Series, pp. 203-210.
[14]. Saxena, N., Dutta, S., and Pandey, N. (2016).
“Implementation of Asynchronous Pipeline using
Transmission Gate logic”. International Conference on
Computational Techniques in Information and
Communication Technologies (ICCTICT), pp. 735–740.
[15]. Sjogren, A.E., and Myers, C.J. (2000). “Interfacing
Synchronous and Asynchronous Modules within a High-
Speed Pipeline”. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 8, No. 5, pp. 573–583.
[16]. Yun, K.Y., Beerel, P.A., and Arceo, J. (1996). “High-
Performance Asynchronous Pipeline Circuits”. In
Proceedings Second International Symposium on
Advanced Research in Asynchronous Circuits and Systems,
IEEE Comput. Soc. Press, pp. 17–28.
