References
[1]. N. Ahmed, T. Natarajan, and K.R. Rao, (1974). “Discrete
Cosine Transform”. IEEE Transactions on Computers, Vol. C-
23, No. 1.
[2]. V.S. Rao, P.R. Kumar, G.V.H. Prasad, M.P. Kumar, and S.
Ravichand, (2010). “Discrete Cosine Transform vs. Discrete
Wavelet Transform: An Objective Comparison of Image
Compression Techniques for JPEG Encoder”. International
Journal of Advanced Engineering & Applications.
[3]. Z. Xiong, K. Ramchandran, M.T. Orchard, and Y.-Q.
Zhang, (1999). “A Comparative Study of DCT- and Wavelet-
Based Image Coding”. IEEE Transaction on Circuit and
Systems for Video Technology, Vol. 9, No. 5.
[4]. Reza Ebrahimi Atani, Sattar Mirzakuchaki, Farshid
Samii, and Mohammed Reza Nasrollahzadeh, (2007).
“Design and Implementation of a 157 MHz DA-Based DXT
th Coprocessor ”. 4 IEEGCC Conference, Manama,
Kingdom of Bahrain, 11-14 Nov. 2007.
[5]. Soumik Ghosh, Soujanya Venigalla, and Magdy
Bayoumi, (2005). “Design and Implementaion of a 2D-DCT
Architecture using Coefficient Distributed Arithmetic”.
Proceedings of the IEEE Computer Society Annual
Symposium on VLSI, pp.162 - 166, 11-12 May 2005.
[6]. Payman Samadi, Huappeng Wu, and Majid Ahmadi,
(2006). “The 2-D quantized DCT with Distributed Arithmetic”.
IEEE CCECE/CCGEI, Ottawa, pp. 2049-2052.
[7]. R.E. Atani, M. Baboli, S. Mirzakuchaki, S.E. Atani, and B.
Zamanlooy, (2008). “Design and Implementation of a 118
MHz 2D DCT Processor”. IEEE International Symposium on
Industrial Electronics, pp. 1076-1081.
[8]. M. Jridi and A. Alfalou, (2010). “A Low-power, Highspeed
DCT Architecture for Image Compression: Principle
and implementation”. VLSI System on Chip Conference
(VLSI-SoC), pp. 304-309.
[9]. H.L.P.A. Madanayake, R.J. Cintra, D. Onen, V.S.
Dimitrov, and L.T. Bruton, (2011). “Algebraic Integer based
8×8 2-D DCT Architecture for Digital Video Processing”. IEEE
International Symposium on Circuits and Systems (ISCAS), pp. 1247-1250.
[10]. V. Dimitrov, K. Wahid, and G. Jullien, (2004).
“Multiplication-free 8×8 2D-DCT Architecture using
Algebraic Integer Encoding”. IEE Electronics Letters, Vol. 40,
No. 20, pp. 1310–1311.
[11]. Yogesh M. Jain, Aviraj R. Jadhav, Harish V. Dixit,
Akshay S. Hindole, Jithin R. Vadakoott, and Devendra
Bilaye, (2015). “A Novel VLSI Design of DCTQ Processor for
th FPGA implementation”. 19 International symposium on
VLSI Design and Test (VDAT), IEEE, pp. 1-5.
[12]. P. Vinay Mallik, and G. Hemachandra, (2016).
“Design of 1D-DCT Using 8x8 Vedic Multiplier”. International
Journal of Engineering Science and Computing, Vol. 6,
No. 6, pp. 6345-6348.
[13]. V. Satyakishore, J.E.N. Abhilash and G.N.V.
Ratnakishor, (2014). “ FPGA Implementation &
Performance Comparision of Various High Speed unsigned
Binary Multipliers using VHDL”. International Journal on
Recent and Innovation Trends in Computing and
Communication, Vol. 4, No. 11, pp. 3936–3940.