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Implementation of SDC Using I²C Multi Master-Multi Slave with Wishbone Signal

Nandini*, K. Nagi Reddy**

* PG Scholar, Department of Digital Electronics and Communication Systems, NBKR Institute of Science & Technology, Vidyanagar, India.

** Professor, Department of Electronics and Communication Engineering, NBKR Institute of Science & Technology, Vidyanagar, India.

Periodicity:May - July'2016
DOI : https://doi.org/10.26634/jcs.5.3.8064

Abstract

I²C Multi Master with Multi Slave is designed from a bidirectional serial data bus containing bidirectional data lines like Serial Data Line (SDL) and Serial Clock Line (SCL) along with Wishbone Signal. I²C protocol has the ability to support multiple masters and provides an efficient method of data exchange between devices. This is a very useful protocol for faster devices to communicate each other with slower devices without data loss. With the use of this protocol, a serious problem arises resulting to overlapping of signals. To overcome such problems, a special signal called WishBone signal is used. The main objective of this paper is to observe the operation of the master controller and wishbone controller, which performs high speed data transfer in the presence of master or slave. This yields higher speed data transfer over the network. The complete module is modeled in Verilog HDL and synthesized in Xilinx 13.2i, also simulated in Model Sim 6.4a.

Keywords

I2C (or IIC, Inter Integrated Circuit), WishBone, SCL (Serial Clock Line), SDA (Serial Data Line), Master, Slave, Xilinx, Model Sim 6.4a

How to Cite this Article?

Nandini, G., and Reddy, K.N. (2016). Implementation of SDC Using I²C Multi Master-Multi Slave with Wishbone Signal. i-manager’s Journal on Communication Engineering and Systems, 5(3), 21-26. https://doi.org/10.26634/jcs.5.3.8064

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Implementation of SDC Using I2C Multi Master-Multi Slave with Wishbone Signal