In this paper, a Dual Loop PLL has been designed. In the proposed design, a DL-PLL is designed in two ways. The first method is, that the two PLLs are connected to a mixer and in the second method, the two PLLs are directly cascaded. The two designs will give better results, when compared with the normal CP-PLL. The proposed DL-PLL consists of an AND based PFD and a CP circuit with switching scheme, such that the proposed PFD eliminates the missing edge and phase ambiguity problems in the conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and the charge injection error problem with this new design technique. By using the normal CP-PLL, the total noise performance will be -91.134 dB/Hz and the power dissipation will be 357831.4 mW. By using the DL-PLL with a mixer, the power dissipation will be reduced to 4.2005 mW, but the total noise performance will be somewhat good. By using the second type of DL-PLL that is by directly cascading two PLLs, the power dissipation is reduced to 2.581 mW and the total noise performance will be -133.93 dBc/Hz at 100 MHz offset frequency for a load capacitance of 0.01 μF. The current noise of the PFD and CP circuit has been measured from the transistor level simulation to find the phase noise of the Dual Loop PLL, for output frequency of 2.4 GHz with 100 MHz reference signal in Hspice (Hspui) using awan waves and HSPICE RF Tool. The proposed Dual Loop PLL will have an improved noise performance of -42 dB when compared to the existing charge pump PLL circuits. In addition, the total noise and power dissipation modeling has been done to find the output total noise and Power dissipation of the PLL, considering the PFD and CP output current noise measured at the transistor level in 0.18 μm CMOS.