Day by day the size of systems & application software is increasing, demanding huge memory. Movement of high volume information among various parts of computing system pays an important role as a factor to the overall power budget. Consumption of power has become an important issue for modern COMPUTING systems [1]. Suggested way is to reduce power consumption is to reduce a bus activities [2] Power consumption due to communication on system-level buses contributes a lot for overall power requirement. Various coding schemes have been proposed in literature to encode data to reduce the number of bus transition [3][4][5]. The paper aims at providing a framework for evaluation of one of the popular Bus encoding algorithms for 4-bit information flowing in computing system. Architectural exploration of a system design has been considered to focus on the power consumption estimation of memory communication as well as other components of system. Result shows that off chip busses consumes considerable amount of power. FVS / FV-MSB, BIC gives reduction of 50% reduction in I/O information movement average power dissipation and 25% reduction in I/O average power dissipation. We have also evaluated segmentation concept with analysis of all bits of channel. We find that Bus segmentation requires redefinition unlike the conventional one.