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A Review on Optimized FFT/IFFT Architectures for OFDM Systems

E. Sujatha*, 0**, M. N. Giri Prasad***, N. Padmaja****

* Research Scholar, Department of Electronics and Communication Engineering, JNTUA, Ananthapuramu, India.

**,**** Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.

*** Professor, Department of Electronics and Communication Engineering, JNTUA, Ananthapuramu, India.

Periodicity:October - December'2015
DOI : https://doi.org/10.26634/jwcn.4.3.4849

Abstract

This paper surveys, the widely adopted architectures of FFT/IFFT processor for MIMO OFDM systems. Emerging trends in mobile communication pose many architectural challenges to achieve high data throughput, less hardware complexity, low power consumption, high speed MIMO-OFDM systems. FFT/IFFT processor is one of the highest computational complexity modules in the system, to meet IEEE 802.11n requirements. The main concern of application of pipeline FFT/IFFT architectures is performance and power reduction. At the same time, application of memory based FFT/IFFT architectures are preferred when complexity is a main concern. High throughput rate can be achieved by the use of parallel data path schemes and higher radix and mixed radix FFT algorithms are used to reduce power consumptions and hardware complexity of the OFDM system. The unfolding mixed radix multipath delay feedback FFT architecture is used to deal efficiently with multiple data sequences. In Single-path delay feedback style, a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor for low power consumption. This paper presents a comparative study on different efficient pipeline FFT/IFFT processor for OFDM applications in terms of scope of optimization and hardware complexity. Finally, this survey paper suggests open research challenges in this emerging area.

Keywords

802.11n, Fast Fourier Transform (FFT), Inverse Fast Fourier Transform (IFFT), Multiple-Input Multiple-Output (MIMO),Orthogonal Frequency DivisionMultiplexing (OFDM).

How to Cite this Article?

Sujatha, E., Subhas, C., Giri Prasad, M. N., and Padmaja, N. (2015). A Review on Optimized FFT/IFFT Architectures for OFDM Systems. i-manager's Journal on Wireless Communication Networks, 4(3), 33-39. https://doi.org/10.26634/jwcn.4.3.4849

References

[1]. S. Magar, S. Shen, G. Luikuo, M. Fleming, and R. Aguilar, (1988). An application specific DSP chip set for 100-MHz data rates”.in Proc. Int. Conf.Acoustics, Speech, Signal ProcessVol. 4, pp. 1989-1992.

[2]. H. Shousheng and M. Torkelson, (1998), “Designing pipeline FFT processor for OFDM (de)modulation”.in Proc URSI Int. Symp. on Signals, Syst.Electron, Vol. 29, pp. 257- 262.

[3]. J. O’Brien, J. Mather, and B. Holland, (1989). “A 200 MIPS single-chip 1 k FFT processor”. in Proc. IEEE Int. Solid-State Circuits Conf, Vol. 36, pp. 166-67, 327.

[4]. B. M. Bass, (1999). “A low-power, high-performance, 1024-point FFT processor”. IEEE J. Solid-State Circuits, Vol. 34, No. 3, pp. 380 - 387.

[5]. Y.W. Lin, H.Y. Liu and C.Y. Lee, (2004). “A dynamic scaling FFT processor for DVB-T applications”. IEEE J. Solid-State Circuits, Vol. 39, No. 11, pp. 2005 - 2013.

[6]. Chun-Lung Hung, Syu-Siang Long, and Muh-Tian Shiue, (2009). ”A Low Power and Variable-Length FFT Processor Design for Flexible MIMO OFDM Systems”. IEEE International Symposium on Circuits and Systems, ISCAS.

[7]. Jea Hack Lee, Eun Ji Kim, and Myung Hoon Sunwoo, (2012). “Low Complexity FFT/IFFT Processor for High-speed OFDM System using Efficient Multiplier Scheduling”. IEEE International Symposium on Circuits and Systems (ISCAS).

[8]. Yu-Wei Lin and Chen-Yi Lee, (2007). “Design of an FFT/IFFT Processor for MIMO OFDM Systems”. IEEE Transactions On Circuits And Systems—I:Regular Papers, Vol. 54, No. 4.

[9]. Y.W. Lin, H.Y. Liu and C.Y. Lee, (2005). “A 1 GS/s FFT/IFFT processor for UWB applications”. IEEE J. Solid-State Circuits, Vol. 40, No. 8, pp. 1726 - 1735.

[10]. W.C. Yeh and C.W. Jen, (2003). “High-speed and low-power split-radix FFT”. IEEE Trans. Acoust., Speech, Signal Process, Vol. 51, No. 3, pp. 864 - 874.

[11]. M. Jaber and D. Massicotte, (2009). “A new FFT concept for efficient VLSI implementation: Part I – Butterfly processing element”. in Proc. IEEE Int. Conf. Digital Signal Processing, pp.1- 6.

[12]. Taesang Cho, Hanho Lee, Jounsup Park and Chulgyun Park, (2011). “A High-Speed Low-Complexity Modified Radix-25 FFT Processor for Gigabit WPAN Applications”. IEEE International Symposium on Circuits and Systems (ISCAS).

[13]. R. I. Hartley, (1996). “Subexpression sharing in filters using canonic signed digit multipliers”. IEEE Trans. Circuits Syst. II, Vol. 43, No.10, pp. 677 - 688.

[14]. S. Huang and S. Chen, (2010). "A Green FFT Processor with 2.5-GS/s for IEEE 802.15.3c (WPANs)”. in Proc. of 2010 International Conference on Green Circuits and Systems (ICGCS), pp.9 -13.

[15]. N. Padmaja and E.Ramyakrishna (2015). “HHT and DWT Based MIMO-OFDM for Various Modulation Schemes: A Comparative Approach”. i-manager's Journal on Wireless Communication Networks, Vol. 4, No. 2.

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