In this paper, design and implementation of a low power inverse SINC filter (ISF) is described. The proposed ISF is designed to compensate for SINC distortion and maintain flat output amplitude over the bandwidth of 0 to 80% of the first Nyquist zone. In order to reduce circuit area and power consumption, a modified canonic signed digit (MCSD) algorithm is used to replace multiplications with additions, subtracts, and logic shift. In addition, binary shifts are replaced by hardwiring without using any logic gates. The circuit area required for MCSD multiplication is thus approximately proportional to the number of adders and subtractors. Since the impulse response of this filter is symmetrical relative to the centre, the filter is further simplified by adding the symmetrical taps outputs together before the “multiplications”. The proposed ISF is implemented in 0.18µm CMOS technology. With the filter length equal to 9 and input/output interfaces set to 12 bits, the power consumption of the core area is 2.785 mW when clock frequency is 50 MHz, and 8.342 mW when clock frequency is 150 MHz.