Circuit Merging Versus Dynamic Partial Reconfiguration - The HoMade Implementation

Jean Perier*, Wissem Chouchene**, Jean-Luc Dekeyser***
* Student, Polytechnic Paris, France.
** Research scholar, University of Sciences and Technologies, France.
*** Professor, Department of Computer Science, University of Sciences and Technologies, France
Periodicity:February - April'2015
DOI : https://doi.org/10.26634/jes.4.1.3691

Abstract

One goal of reconfiguration is to save power and the occupied resources. In this paper, we compare two different kinds of reconfiguration available on Field-Programmable Gate Arrays (FPGA) and authors discuss their pros and cons. The first method that we study is circuit merging. This type of reconfiguration methods consists of sharing common resources between different circuits. The second method that we explore is Dynamic Partial Reconfiguration (DPR). It is specific to some FPGA, allowing well defined reconfigurable parts to be modified during run-time. Authors show that DPR, when available, has good and more predictable result in terms of occupied area. There is still a huge overhead in terms of time and power consumption during the reconfiguration phase. Therefore, authors show that circuit merging remains an interesting solution on FPGA because it is not vendor specific and the reconfiguration time is around a clock cycle. Besides, good merging algorithms exist even-though FPGA physical synthesis flow makes it hard to predict the real performance of the merged circuit during the optimization. We establish the comparison in the context of the HoMade processor.

Keywords

FPGA, Partial Dynamic Reconfiguration, Circuit Merging, Softcore.

How to Cite this Article?

Perier,J., ,Chouchene,W., and Dekeyser,J. (2015). Circuit Merging Versus Dynamic Partial Reconfiguration - The H Made Implementation. i-manager’s Journal on Embedded Systems, 4(1), 14-23. https://doi.org/10.26634/jes.4.1.3691

References

[1]. Xilinx corporation., “Dynamic and partial reconfiguration” Retrieved from http://www.xilinx.com /tools/partial-reconfiguration.html
[2]. Micro Blaqe, (2011). “MicroBlaze Processor Reference Guide UG081”.
[3]. S. A. Cook, (1971) “The complexity of theorem-proving procedures”, In Proceedings of the third annual ACM symposium on Theory of Computing, pp. 151–158.
[4]. C. Wolinski, K. Kuchcinski, E. Raffin, and F. Charot, (2009). “Architecture-Driven Synthesis of Reconfigurable Cells”, in 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD '09, pp. 531-538.
[5]. S. O. Memik, G. Memik, R. Jafari, and E. Kursun, (2003). “Global Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs”, In Proceedings of the 40th Annual Design Automation Conference, New York, NY, USA, 2003, p. 604–609.
[6]. N. Moreano, E. Borin, C. D Souza, and G. Araujo, (2005). “Efficient datapath merging for partially reconfigurable architectures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No 7, pp. 969-980, Juill.
[7]. P. Brisk, A. Kaplan, and M. Sarrafzadeh, (2004), “Areaefficient Instruction Set Synthesis for Reconfigurable System-on-chip Designs”, In Proceedings of the 41st Annual Design Automation Conference, New York, NY, USA, pp. 395–400.
[8]. S. Raje et R. A. Bergamaschi, (1997) “Generalized Resource Sharing”, In Proceedings of the 1997 IEEE/ACM International Conference on Computer-aided Design, Washington, DC, USA, p. 326–332.
[9]. Z. Huang, S. Malik, N. Moreano, and G. Araujo (2004), “ The Design of Dynamically Reconfigurable Datapath Coprocessors ”, ACM Trans. Embed. Comput. Syst., Vol. 3, No 2, p. 361–384, mai 2004.
[10]. K. Kuchcinski, (2003). “Constraints-driven Scheduling and Resource Assignment”, ACM Trans. Des. Autom. Electron. Syst., Vol. 8, No 3, p. 355–383, juill.
[11]. Xilinx corporation, “Reconfiguring User Logic Using Custom ICAP Processor and Monitoring ICAP Signals Using ChipScope Core Lab”, in http://forums.xilinx.com/ xlnx/attachments/xlnx/EDK/23008/1/lab04.pdf
[12]. Xilinx corporation, “Driving ICAP Resource”, Retrieved from http://home.mit.bme.hu/~feher/ Reconf_Comp/10_Driving_ICAP.pdf
[13]. Xilinx Inc., (2006). “OPB_HWICAP (v1.00.b) Product Specification”, DS280, Jul.
[14]. F. Duhem, F. Muller, and P. Lorenzini, (2011). “FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Over head on FPGA” , "Reconfigurable Computing: Architectures, Tools and Applications, pp. 253-260,
[15]. Robin Bonamy, Hung-Manh Pham, Sebastien Pillement, and Daniel Chillet, (2012). “UPaRC—Ultra-fast power-aware reconfiguration controller ”, Design, Automation & Test in Europe Conference & Exhibition (DATE),
[16]. Hung-Manh Pham, Van-Cuong Nguyen, and Trong- Tuan Nguyen, (2012). “DDR2/DDR3-based ultra-rapid reconfiguration controller ”, Communications and Electronics (ICCE), Fourth InternationalConference on DOI: 10.1109/CCE.2012.6315949 -2012.
[17]. Xilinx, Inc, (2011). “\Logicore ip multi-port memory controller (mpmc)(ds643 v6.03.a),".
[18]. V. Manohararajah, G. R. Chiu, D. P. Singh, and S. D. Brown, (2006). “Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow “, In Proceedings of the 2006 International Workshop on System-level Interconnect Prediction, New York, NY, USA, , pp. 3–8.
[19]. “7 Series FPGAs Memory Interface Solutions User Guide UG586”, March 1, 2011.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.