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An Efficient Carry Skip Adder Based Reduced Complexity RS-Decoder

Abirsha M*, Amsa Sangara Nayagi. P**

* PG Graduate, Department of Electronics and Communication Engineering, KNSK College of Engineering, Kanyakumari, Tamilnadu, India.

** Assistant Professor, Department of Electronics and Communication Engineering, KNSK College of Engineering, Kanyakumari, Tamilnadu, India

Periodicity:December - February'2015
DOI : https://doi.org/10.26634/jcom.2.4.3330

Abstract

Reed–Solomon (RS) codes are widely used in digital communication and storage systems. In this paper the authors present a high-speed low-complexity Reed–Solomon (RS) decoder architecture using low power carry skip adder. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This reduces the active power. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. A 32-bit carry skip adder is used in the proposed method. Our approach has been implemented in 130 nm CMOS (Complementary Metal Oxide Semiconductor) technology. Compared to the previous designs, the adder architecture decreases the computational complexity with similar or higher coding gain. The 40-bit adder's average power dissipation normalized to 600 MHz operation as 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

Keywords

Reed–Solomon (RS) Codes, Unified Syndrome Computation (USC), Low Power Carry Skip Adder, Carry Look- Ahead Logic.

How to Cite this Article?

Abirsha, M., and Nayagi, P.A.S. (2015). An Efficient Carry Skip Adder Based Reduced Complexity RS-Decoder. i-manager’s Journal on Computer Science, 2(4), 18-24. https://doi.org/10.26634/jcom.2.4.3330

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