Fault-Tolerant Dynamic Adaptive Routing in NoC

Anandeswari. S.A*, Amsa Sangara Nayagi. P**
* PG Student, KNSK College of Engineering, Kanyakumari, Tamilnadu, India.
** Assistant Professor, KNSK College of Engineering, Kanyakumari, Tamilnadu, India.
Periodicity:December - February'2015
DOI : https://doi.org/10.26634/jcom.2.4.3329

Abstract

Network-on-Chip (NoC) is a scalable and flexible communication medium for the design of multi-core based Systemon- Chip (SoC). Communication performance of NoC depends heavily on efficient routing algorithms. Dynamic routing is desirable because of its substantial improvement in communication bandwidth and intelligent adaptation to faulty links and congested traffic. In this paper, the authors propose a fault tolerant Dynamic Adaptive Routing in Networks-on- Chip (NoCs). This algorithm can be implemented on routing to detect transient and permanent faults in the network. That means the packet is able to move around the faults to their destination with a non-minimum path. In addition, the multilevel congestion control mechanism gives the ability to distribute the load and to avoid the faults. Because this procedure is based on adaptive routing, the hardware overhead and computational times are minimal. Experimental results based on an actual Verilog implementation demonstrate that the proposed dynamic adaptive routing algorithm improves the network throughput significantly compared to traditional algorithms.

Keywords

Dynamic Adaptive Routing, Network-on-Chip (NoC), Transient Fault, Permanent Fault, System-on-Chip (SoC).

How to Cite this Article?

Anandeswari, S.A., and Nayagi, P.A.S. (2015). Fault-Tolerant Dynamic Adaptive Routing in NoC. i-manager’s Journal on Computer Science, 2(4), 12-17. https://doi.org/10.26634/jcom.2.4.3329

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