As technology trends advances, workstation chips become increasingly parallel, and efficient communication substrate is decisive for meeting performance and energy targets. Also as nano technology shrinks day by day work station chips are migrated to SOIC – System On Integrated Chip, which leads to many challenges in the design era, and is more critical for communication applications such as Network on Chip (NoC) and also as technology shrinks, the power supply of NoC links starts to struggle with that of NoC routers. In this paper, the authors propose the use of efficient data encoding techniques as a practical way to reduce both power dissipation and energy consumption of NoC links. In this work, the authors target the core cause of network energy consumption through techniques that reduce link and router-level switching commotion. The proposed encoding techniques are simulated and verified by Xilinx tools along with Virtex – 5 FPGA board.