References
[1]. Koji Sakui et. al. (1988). A New Static Memory Cell
Based on Reverse Base Current (RBC) Effect of IBipolar
Transistors, IEDM, IDigest of Technical Papers, pp. 44-47.
[2]. J. P. A. van der Wagt, A. C. Seabaugh, and E. A.
Beam, III, (1996). “RTD/HFET low standby power SRAM gain
cell,” in IEDM Tech. Dig., pp.425–428.
[3]. J. Y.C. Sun, "CMOS Technology for 1.8V and Beyond",
(1997). International Symposium on VLSI Technology,
Systems and Applications, Digest of Technical Papers, pp.
293-297.
[4]. E. Goto, K. Mutara, K. Nakazawa, T. Moto-Oka, Y.
Matsuoka, Y. Ishibashi, T. Soma, and E. Wada, (1960).
“Esaki diode high-speed logical circuits”, IRE Trans.
Electron. Comput., Vol. 9, No.1, pp. 25-29.
[5]. H. Goto, H. Ohkubo, K. Kondou, M. Ohkawa, N.
Mitani, S. Horiba, M. Soeda, F. Hayashi, Y. Hachiya, T.
Shimizu, M. Ando, and Z. Matsuda, (1992). “A 3.3-V 12-ns
16-Mb CMOS SRAM,” IEEE J. Solid-State Circuits, Vol. 27,
No 11. pp.1490-1496.
[6]. A. C. Seabaugh and R. Lake, (1998), “Tunnel diodes”
Encyclop. Phys., Vol. 22, pp. 335-359.
[7]. A. Seabaugh, B. Brar, T. Broekaert, G. Frazier, P. van
der Wagt, and E. Beam, III, (1997). “Resonant tunneling
circuit technology: Has it arrived?,” in GaAs IC Symp. Tech.
Dig., pp. 119-122.
[8]. J. P. A. van der Wagt, A. C. Seabaugh, G. Klimeck, E.
A. Beam, III, T. B. Boykin, R. C. Bowen, and R. Lake (1997).
“Ultralow current-density RTD's for tunneling-based SRAM,”
th in Proc. 24 Int. Symp. pp. 601-604.
[9]. J. P. A. van der Wagt, H. Tang, T. P. E. Broekaert, and E.
A. Beam, III, (1996). “Vertical multi-bit resonant tunneling
diode memory cell,” in Device Res. Conf. Tech. Dig., ISBN:
0-7803-3358-6 , pp. 168–169.
[10]. J. P. A. van der Wagt, (1999). “Tunneling-based
SRAM,” in Proc. IEEE, Vol. 87, No. 4, pp. 571–595.
[11]. V. George et al., (2007). "Penryn: 45-nm next
generation Intel core 2 processor," IEEE Asian Solid-State
Circuits Conference, pp.14-17.
[12]. Yih Wang et al., (2008). "A 1.1 GHz 12 µA/Mb-
Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS
Technology With Integrated Leakage Reduction for
Mobile Applications," IEEE Journal of Solid-State Circuits,
Vol.43, No.1, pp.172-179.
[13]. K. Karda et al., (2012). ” Bistable-Body Tunnel SRAM”,
IEEE Transactions on nanotechnology, Vol. 11, No. 6,
pp.1067-1072.
[14]. “Predictive technology model” version 2.1 for high
performance 32nm node. Using high-k, metal gate and
stress”. http://www.eas.asu.edu/~ptm/, accessed: 08-31-
09.
[15]. K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, (2003).
“16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for
handling cosmic-ray-induced multi-errors,” IEEE Int. Solid-
State Circ. Conf. (ISSCC) , pp. 302–303.
[16]. S. Natarajan, et al. (2008). "A 32nm logic technology
featuring 2nd-generation high-k + metal-gate transistors,
enhanced channel strain and 0.171µm2 SRAM cell size in
a 291Mb array," IEEE IEDM Tech. Dig., pp.1-4.
[17]. T. Ohsawa et al., (2002). “Memory design using a
one-transistor gain cell on SOI,” IEEE J. Solid-State Circ.,
Vol. 37, No. 11, pp. 1510-1522.
