Fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and speed of the DSPs is mainly determined by the speed of its multipliers. Multiplication is the most fundamental operation with intensive arithmetic computations. Now a days, embedded systems are used for wide range of such applications. The power consumption, performance, and demanding security are the main issues in designing systems. To achieve this, authors combined the sub-threshold operation and charge recovery techniques. Using the technique, lower power consumption, ability of operating at higher frequencies, and more security than the existing logic circuits are achieved. Different methods of algorithms are used in multipliers to increase the performance. In this paper, 4*4 adiabatic multiplier versus 4*4 two phase clocking sub threshold adiabatic multiplier using Vedic mathematics are implemented. The power dissipation of two phase clocking sub threshold adiabatic is low when compared to their adiabatic multipliers. This paper is implemented in HSPICE using 0.18μm CMOS process technology.