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Low Power and Area Efficient Architecture of Pulse Shaping FIR Filter For Digital Up Converter

I. Vinodhini*, M. Thangavel**

* PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, India.

** Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.

Periodicity:August - October'2014
DOI : https://doi.org/10.26634/jcs.3.4.3224

Abstract

FIR filters are widely used in wireless mobile communication systems such as channel equalization, matched filtering, and pulse shaping, due to their stability and reconfigurability. In this paper, the pulse shaping FIR filter such as root-raised cosine filter is designed for multistandard digital up converter. The two bit binary common sub-expression based binary common sub-expression elimination algorithm is used to ignore the occurrences in identical bit pattern. The number of additions and multiplications are reduced using this technique. Carry save adder is used to generate the partial product which reduces the area and increases the speed. The area and speed of the filter design is synthesized and simulated using Xilinx ISE 12.1.

Keywords

Reconfigurability, pulse shaping FIR filter, Carry Save Adder, Digital up converter.

How to Cite this Article?

Vinodhini, I., and Thangavel, M. (2014). Low Power and Area Efficient Architecture of Pulse Shaping Fir Filter For Digital Up Converter. i-manager’s Journal on Communication Engineering and Systems, 3(4), 8-14. https://doi.org/10.26634/jcs.3.4.3224

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