The quantum cellular automata is the basis for computing Nanotechnology based designs. The QCA cells are based on cells of coupled quantum dots that are featured at nanometer scale. As multipliers are the major computing elements in any arithmetic unit, several designs have emerged to improve performance, decrease area and consume less power. The tree based structures prove better designs of multipliers when compared to conventional designs. In this paper, a 4x4 Wallace tree multiplier is developed using majority gate structures. The design is developed using Verilog HDL and are functionally verified using ISIM simulator. The synthesis is carried out in Xilinx ISE synthesizer and the results are proved to be optimized in terms of delay and area.