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An Efficient Low Power Multiplier Using SubthresholdAdiabatic Logic

Tounga Mounika*, Duvvuru Praveen Kumar**, M. Bharathi***

*,** M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.

*** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupathi.

Periodicity:June - August'2014
DOI : https://doi.org/10.26634/jcir.2.3.3161

Abstract

Multiplication Algorithms have considerable effect on processors’ performance. Multiplier is an important circuit used in electronic industry especially in Digital Signal Processing operations such as filtering, convolution and analysis of frequency. There are different types of algorithms used in multipliers to achieve the better performance. In this paper, 8*8 Wallace Tree and Dadda multipliers are implemented using two phase clocking subthreshold adiabatic logic. Its power dissipation is less when compared to their respective 8*8 CMOS multipliers. This paper can be implemented in HSPICE using 0.18μm CMOS standard process technology

Keywords

VLSI (Very Large Scale Integration), HSPICE (Hewlett Simulation Program with Integrated Circuit Emphasis), CMOS (Complementary Metal Oxide Semiconductor)

How to Cite this Article?

Mounika, T., Kumar, D. P., and Bharathi, M. (2014). An Efficient Low Power Multiplier Using Subthreshold Adiabatic Logic. i-manager’s Journal on Circuits and Systems, 2(3), 7-11. https://doi.org/10.26634/jcir.2.3.3161

References

[1]. Yasuhiro Takahashi and Toshikazu Sekine, (2014). “Two Phase Clocking Subthreshold Adiabatic Logic”. Circuits and Systems, (ISCAS), 2014 IEEEE)pp.598-60

[2]. Praveen Kumar Duvvuru and Bhaathimuni (2014). “A High speed floating point multiplier using vedic mathematics”, i-manager's Journal on Circuits and Systems, Vol. 2, No.2 , pp.1-9.

[3]. C.S.Wallace (2001). “A suggestion for a fast multiplier,” IEEE Trans. Electron.Comput., Vol. EC-13, No. 1, pp. 14–17.

[4]. Anju S and Saravanan (2013). “High performance dadda multiplier implementation using high speed carry select adder”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 2, No. 3. pp.1572-1575

[5]. P.Samundiswary and K.Anitha (2013). “Design and Analysis of CMOS Based DADDA Multiplier”, IJCEM International Journal of Computational Engineering & Management, Vol. 16, No. 6, pp.12-17

[6]. “Wallace Tree Multiplier and Dadda Mulitiplier” www.wikipedia.com

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