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Dual Tail Inverter based Comparator Design with Sub Threshold Voltage

T. Swarna Latha*, T. Suguna**

* Assistant Professor, Sri Sai Institute of Technology & Science, Rayachoti, Kadapa.

** Assistant Professor, Adithya College of Engineering, Madanapalli, Chittoor.

Periodicity:February - April'2014
DOI : https://doi.org/10.26634/jcs.3.2.2936

Abstract

A new CMOS dynamic comparator using dual input, single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with a dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two crosses, coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, and noise immunity. The simulation results will be shown on the W-Edit; average power consumption is in the T-spice.

Keywords

CMOS Comparator, Low Power, High Speed, Analog-to-Digital Converter and Tanner EDA, Complementary Metal Semiconductor (CMOS)

How to Cite this Article?

Latha, T. S., and Suguna, T. (2014). Dual Tail Inverter Based Comparator Design with Sub Threshold Voltage. i-manager’s Journal on Communication Engineering and Systems, 3(2), 33-39. https://doi.org/10.26634/jcs.3.2.2936

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