The RSA system is widely employed in networking applications for good performance and high security. It supports the multiple key sizes like 128 bits, 256 bits, 512 bits. In this paper, The authors use Verilog code to implement a 16-bit RSA block cipher system. Therefore it can easily be fit into the different systems requiring different levels of security. The whole implementation includes three parts: key generation, encryption and decryption process. The key generation stage aims to generate a pair of public key and private key, and then the private key will be distributed to receiver according to certain key distribution schemes. The memory usage and overhead associated with the key generation is eliminated by the proposed system model. The cipher text can be decrypted at receiver side by RSA secret key. Verilog code is synthesized and simulated using Xilinx-ISE 12.1. It is verified that this architecture supports for multiple key of 128bits, 256bits, and 512 bits. Net list generated from RTL Compiler will be used to generate the IC layout. In this work, they have also developed an algorithm using LabVIEW 2010. LabVIEW (Laboratory Virtual Instrument Engineering Workbench) is a graphical programming language that uses icons instead of lines of text to create programs. Unlike text based programming language, LabVIEW uses the data flow programming, where the flow of data determines the execution. The flexibility, modular nature and ease to use programming is possible with LabVIEW, making it less complex.