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FPGA Based Convolution Encoder Time Domain and State machine design Using VHDL

S P Kurlekar*

Assistant Professor, Department of Electronics &Tele Communications Engineering, (SITCOE, Yadrav) Maharashtra, India.

Periodicity:January - March'2014
DOI : https://doi.org/10.26634/jdp.2.1.2723

Abstract

When the errors introduced by the information channel are unacceptable then the channel coding is needed. The use of channel coders with source coders provides the efficient and reliable transmission in the presence of noise. The use of channel coders with source coders provides the efficient and reliable transmission in the presence of noise. Coding permits an increased rate of information transfer at a fixed error rate, or a reduced error rate for a fixed transfer rate. A convolution coder accepts a fixed number of message symbols and produces a fixed number of code symbols, but its computations depends not only on the current set of input symbols but also on some of previous input symbols.[1] Through this paper we have illustrated design of convolution encoder using time domain approach with VHDL platform. The target technology is used as Sparten FPGA device.

Keywords

VHDL,FPGA

How to Cite this Article?

Kurlekar.S.P. (2014), FPGA Based Convolution Encoder Time Domain And State Machine Design Using VHDL. i-manager’s Journal on Digital Signal Processing, 2(1), 33-36. https://doi.org/10.26634/jdp.2.1.2723

References

[1]. Viterbi.A.J, (1971). "Convolution codes and their performance in communication systems," IEEE Transaction on Communications, Vol.com-19, pp. 751 to 771.

[2] Wong, Y., Jian, W., HuiChong, O., Kyun, C., Noordi, N. (2009). “Implementation of Convolutional Encoder and Viterbi Decoder using VHDL”, Proceedings of IEEE International conference on Research and Development Malaysia.

[3] Serkan Sozen “A Viterbi Decoder Using System C for Area Efficient VLSI Implementation”

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