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Digitally Controlled Delay lines Using Strobe Controlled Logic

N. Manimekalai*, A. Lelina Devi**

* II-ME VLSI Design, Department of ECE, Knowledge Institute of Technology, Salem, India.

** Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India.

Periodicity:January - March'2014
DOI : https://doi.org/10.26634/jdp.2.1.2721

Abstract

In recent years, Digitally Controlled Delay-Lines (DCDL) is a key block in number of applications and play the role of DAC in traditional circuits. This paper presents a totally glitch free DCDL which overcame the limitation of a NAND based DCDL using strobe control method. Using this logic a clock is presented, that reduces the output jitter when compared to the existing method. The existing method uses a delay control code and reduces the delay of about 40%, but it consumes more power and less area efficient. By using strobe controlled logic, the peak to peak absolute output jitter of 70-80% were reduced. As an example application, All-digital spread-spectrum clock generator (SSCG), All-digital phase-locked loops (ADPLL), Phase-locked loop (PLL) were used.

Keywords

All-digital delay-locked loop (ADDLL), all-digital phase-locked loop (ADPLL).

How to Cite this Article?

Manimekalai.N., and Devi,L.A. (2014). Digitally Controlled Delay Lines Using Strobe Controlled Logic. i-manager’s Journal on Digital Signal Processing, 2(1), 22-25. https://doi.org/10.26634/jdp.2.1.2721

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